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Intel StrataFlash(R) Wireless Memory (L18)
28F640L18, 28F128L18, 28F256L18
Datasheet
Product Features
High performance Read-While-Write/Erase -- 85 ns initial access -- 54 MHz with zero wait state, 14 ns clock-todata output synchronous-burst mode -- 25 ns asynchronous-page mode -- 4-, 8-, 16-, and continuous-word burst mode -- Burst suspend -- Programmable WAIT configuration -- Buffered Enhanced Factory Programming (BEFP) at 5 s/byte (Typ) -- 1.8 V low-power buffered programming at 7 s/byte (Typ) Architecture -- Asymmetrically-blocked architecture -- Multiple 8-Mbit partitions: 64-Mbit and 128Mbit devices -- Multiple 16-Mbit partitions: 256-Mbit devices -- Four 16-Kword parameter blocks: top or bottom configurations -- 64-Kword main blocks -- Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE) -- Status Register for partition and device status Power -- VCC (core) = 1.7 V - 2.0 V -- VCCQ (I/O) = 1.35 V - 2.0 V, 1.7 V - 2.0 V -- Standby current: 30 A (Typ) for 256-Mbit -- 4-Word synchronous read current: 15 mA (Typ) at 54 MHz -- Automatic Power Savings mode
Security -- OTP space: * 64 unique factory device identifier bits * 64 user-programmable OTP bits * Additional 2048 user-programmable OTP bits -- Absolute write protection: VPP = GND -- Power-transition erase/program lockout -- Individual zero-latency block locking -- Individual block lock-down Software -- 20 s (Typ) program suspend -- 20 s (Typ) erase suspend -- Intel(R) Flash Data Integrator optimized -- Basic Command Set (BCS) and Extended Command Set (ECS) compatible -- Common Flash Interface (CFI) capable Quality and Reliability -- Expanded temperature: -25 C to +85 C -- Minimum 100,000 erase cycles per block -- ETOXTM VIII process technology (0.13 m) Density and Packaging -- 64-, 128-, and 256-Mbit density in VF BGA packages -- 128/0 and 256/0 density in SCSP -- 16-bit wide data bus
The Intel StrataFlash(R) wireless memory (L18) device is the latest generation of Intel StrataFlash(R) memory devices featuring flexible, multiple-partition, dual operation. It provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 V lowvoltage, multi-level cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows a system to interleave code operations while program and erase operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system designers to choose the size of the code and data segments. The L18 wireless memory device is manufactured using Intel 0.13 m ETOXTM VIII process technology. It is available in industrystandard chip scale packaging.
Order Number: 251902, Revision: 009 April 2005
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Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2005, Intel Corporation. All Rights Reserved.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Contents
1.0 Introduction ............................................................................................................................... 9
1.1 1.2 1.3 Nomenclature ....................................................................................................................... 9 Acronyms .............................................................................................................................. 9 Conventions ........................................................................................................................10
2.0 Functional Overview ............................................................................................................11 3.0 Package Information ............................................................................................................12
3.1 3.2 4.1 VF BGA Packages..............................................................................................................12 SCSP Packages .................................................................................................................14 Signal Ballout......................................................................................................................16 4.1.1 VF BGA Package Ballout.......................................................................................16 4.1.2 SCSP Package Ballout ..........................................................................................18 Signal Descriptions .............................................................................................................19 4.2.1 VF BGA Package Signal Descriptions ...................................................................19 4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions ...........................................21 Memory Map .......................................................................................................................23 Absolute Maximum Ratings ................................................................................................25 Operating Conditions ..........................................................................................................25 DC Current Characteristics .................................................................................................26 DC Voltage Characteristics.................................................................................................27 AC Test Conditions.............................................................................................................28 Capacitance ........................................................................................................................29 AC Read Specifications (VCCQ = 1.35 V - 2.0 V) ............................................................30 AC Read Specifications for 64-Mbit and 128-Mbit Densities (VCCQ = 1.7 V - 2.0 V) .......31 AC Read Specifications for 256-Mbit Density (VCCQ = 1.7 V - 2.0 V) .............................32 AC Write Specifications ......................................................................................................37 Program and Erase Characteristics ....................................................................................41 Power Up and Down ...........................................................................................................42 Reset ..................................................................................................................................42 Power Supply Decoupling...................................................................................................43 Automatic Power Saving.....................................................................................................44 Bus Operations ...................................................................................................................45 9.1.1 Reads ....................................................................................................................46 9.1.2 Writes.....................................................................................................................46 9.1.3 Output Disable .......................................................................................................46
4.0 Ballout and Signal Descriptions......................................................................................16
4.2
4.3 5.1 5.2 6.1 6.2 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8.1 8.2 8.3 8.4 9.1
5.0 Maximum Ratings and Operating Conditions ...........................................................25
6.0 Electrical Specifications .....................................................................................................26
7.0 AC Characteristics ................................................................................................................28
8.0 Power and Reset Specifications .....................................................................................42
9.0 Device Operations.................................................................................................................45
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
9.2 9.3 10.1 10.2 10.3
9.1.4 Standby.................................................................................................................. 46 9.1.5 Reset ..................................................................................................................... 46 Device Commands ............................................................................................................. 47 Command Definitions ......................................................................................................... 48 Asynchronous Page-Mode Read........................................................................................ 50 Synchronous Burst-Mode Read.......................................................................................... 50 10.2.1 Burst Suspend ....................................................................................................... 51 Read Configuration Register (RCR) ................................................................................... 51 10.3.1 Read Mode ............................................................................................................ 52 10.3.2 Latency Count........................................................................................................ 52 10.3.3 WAIT Polarity......................................................................................................... 54 10.3.3.1 WAIT Signal Function ............................................................................ 54 10.3.4 Data Hold............................................................................................................... 55 10.3.5 WAIT Delay............................................................................................................ 56 10.3.6 Burst Sequence ..................................................................................................... 56 10.3.7 Clock Edge ............................................................................................................ 57 10.3.8 Burst Wrap............................................................................................................. 57 10.3.9 Burst Length .......................................................................................................... 57 Word Programming............................................................................................................. 58 11.1.1 Factory Word Programming................................................................................... 59 Buffered Programming........................................................................................................ 59 Buffered Enhanced Factory Programming ......................................................................... 60 11.3.1 Buffered EFP Requirements and Considerations.................................................. 60 11.3.2 Buffered EFP Setup Phase.................................................................................... 61 11.3.3 Buffered EFP Program/Verify Phase ..................................................................... 61 11.3.4 Buffered EFP Exit Phase ....................................................................................... 62 Program Suspend............................................................................................................... 62 Program Resume................................................................................................................ 63 Program Protection............................................................................................................. 63 Block Erase......................................................................................................................... 64 Erase Suspend ................................................................................................................... 64 Erase Resume .................................................................................................................... 65 Erase Protection ................................................................................................................. 65 Block Locking...................................................................................................................... 66 13.1.1 Lock Block ............................................................................................................. 66 13.1.2 Unlock Block .......................................................................................................... 66 13.1.3 Lock-Down Block ................................................................................................... 66 13.1.4 Block Lock Status .................................................................................................. 67 13.1.5 Block Locking During Suspend.............................................................................. 67 Protection Registers ........................................................................................................... 68 13.2.1 Reading the Protection Registers .......................................................................... 69 13.2.2 Programming the Protection Registers.................................................................. 70 13.2.3 Locking the Protection Registers ........................................................................... 70
10.0 Read Operations .................................................................................................................... 50
11.0 Programming Operations .................................................................................................. 58
11.1 11.2 11.3
11.4 11.5 11.6 12.1 12.2 12.3 12.4 13.1
12.0 Erase Operations................................................................................................................... 64
13.0 Security Modes....................................................................................................................... 66
13.2
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
14.0 Dual-Operation Considerations.......................................................................................71
14.1 14.2 Memory Partitioning ............................................................................................................71 Read-While-Write Command Sequences ...........................................................................71 14.2.1 Simultaneous Operation Details ............................................................................72 14.2.2 Synchronous and Asynchronous RWW Characteristics and Waveforms..............72 14.2.2.1 Write operation to asynchronous read transition ...................................72 14.2.2.2 Write to synchronous read operation transition .....................................73 14.2.2.3 Write Operation with Clock Active..........................................................73 14.2.3 Read Operation During Buffered Programming.....................................................73 Simultaneous Operation Restrictions .................................................................................74 Read Status Register..........................................................................................................75 15.1.1 Clear Status Register.............................................................................................76 Read Device Identifier ........................................................................................................76 CFI Query ...........................................................................................................................77
14.3 15.1 15.2 15.3
15.0 Special Read States..............................................................................................................75
Appendix A Appendix B Appendix C Appendix D Appendix E
Write State Machine (WSM) ...........................................................................78 Flowcharts ............................................................................................................85 Common Flash Interface ................................................................................93 Additional Information...................................................................................103 Ordering Information......................................................................................104
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
Revision History
Revision Date 10/15/02 01/20/03 Revision -001 -002 Initial Release Revised 256-Mbit Partition Size Revised 256-Mbit Memory Map Change WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all Writes) Change WAIT function to active during Synchronous Non-Array Read Updated all Waveforms to reflect new WAIT function Revised Section 8.2.2 Added Synchronous Read to Write transition Section Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22 Various text edits Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing Changed ICCS and ICCR values Added 256-Mbit AC Speed Changed Program and Erase Spec Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow Chart Revised Read While Buffered Programming Flow Chart Revised Appendix A Write State Machine Revised CFI Table 21 CFI Identification Various text edits. Various text clarifications, various text edits, block locking state diagram clarification, synchronous read to write timing clarification, write to synchronous read timing clarification Minor text edits Changed Capacitance values Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and Automatic Power Savings Current (typ) Updated Transient Equialent Testing Load Circuit Description
04/11/03 08/04/03
-003 -004
01/20/04 05/22/04
-005 -006
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
09/02/04
-007
Added Table 7 "Bus Operations Summary" on page 45 Modified Table 32 "L18 SCSP Package Ordering Information" on page 105 and added the following order items: * RD48F2000L0YTQ0, RD48F2000L0YBQ0 * RD48F4000L0YTQ0, RD48F4000L0YBQ0 * PF48F3000L0YTQ0, PF48F3000L0YBQ0 * PF48F4000L0YTQ0, PF48F4000L0YBQ0 * NZ48F4000L0YTQ0, NZ48F4000L0YBQ0 * JZ48F4000LOYTQ0, JZ48F4000LOYBQ0 Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm Added mechanical drawing Figure 4 "256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x11x1.0 mm)" on page 15 In Table 32 "L18 SCSP Package Ordering Information" on page 105, corrected 256L18 package size from 8x10x1.2 mm to 8x11x1.2 mm Removed Bin 2 LC and Frequency Support Tables Added back VF BGA mechanical drawings Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP Updated Ordering Info Minor text edits Converted datasheet to new template In Table 4 "Bottom Parameter Memory Map" on page 24, corrected 256-Mbit Blk 131 address range from 100000 - 10FFFF to 800000 - 80FFFF In Section 5.1, "Absolute Maximum Ratings" on page 25, corrected Voltage on any signal (except VCC, VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V In Section E.2, "Ordering Information for SCSP" on page 105, corrected package designators for leaded and lead-free packages from RD/PF to NZ/JZ
09/29/04
-008
04/22/05
-009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
1.0
Introduction
This document provides information about the Intel StrataFlash(R) wireless memory device (L18). This document describes the device features, operation, and specifications.
1.1
Nomenclature
1.8 V: range of 1.7 V - 2.0 V (except where noted) 1.8 V Extended Range: range of 1.35 V - 2.0 V VPP = 9.0 V: VPP voltage range of 8.5 V - 9.5 V Block: A group of bits, bytes or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The Intel StrataFlash(R) Wireless Memory (L18) has two block sizes: 16-Kword, and 64-Kword. Main block: An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block: An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device: Previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. Parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. Bottom parameter device: Previously referred to as a bottom-boot device, a device with its parameter partition located at the lowest physical address of its memory map. Parameter blocks within a parameter partition are located at the lowest physical address of the parameter partition. Partition: A group of blocks that share common program/erase circuitry. Blocks within a partition also share a common status register. If any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. Main partition: A partition containing only main blocks. Parameter partition: A partition containing parameter blocks and main blocks.
1.2
Acronyms
CUI: Command User Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register PR: Protection Register
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
RCR: Read Configuration Register RFU: Reserved for Future Use SR: Status Register WSM: Write State Machine
1.3
Conventions
VCC: signal or voltage connection VCC: signal or voltage level 0x: hexadecimal number prefix 0b: binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of similarly named signals, such as address or data bus. A5: Denotes one element of a signal group membership, such as an address. bit: binary unit byte: eight bits word: two bytes, or sixteen bits Kbit: 1024 bits KByte: 1024 bytes KWord: 1024 words Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
2.0
Functional Overview
The Intel StrataFlash(R) Wireless Memory (L18) provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase, and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The Intel StrataFlash(R) Wireless Memory (L18) allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads do not cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the Intel StrataFlash(R) Wireless Memory (L18) incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the Intel StrataFlash(R) Wireless Memory (L18) supports read operations with VCC at 1.8 volt, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 volt, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the Intel StrataFlash(R) Wireless Memory (L18). An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments. The Intel StrataFlash(R) Wireless Memory (L18) offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The Intel StrataFlash(R) Wireless Memory (L18)'s protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zero-latency block locking and unlocking.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
3.0
3.1
Figure 1.
A1 Index Mark
Package Information
VF BGA Packages
64- and 128-Mbit, 56-Ball VF BGA Package Drawing and Dimensions
A1 Index Mark D S1
1 A B C E D E F G
2
3
4
5
6
7
8 A B C D E
8
7
6
5
4
3
2
1
S2
e F G b
Top View - Ball Side Down
A1 A2 A
Bottom View - Ball Side Up
Seating Plane
Y
Note: Drawing not to scale
Side View
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length (64Mb, 128Mb) Package Body Width (64Mb, 128Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.150 0.325 7.600 8.900
Millimeters Nom Max 1.000 0.665 0.375 7.700 9.000 0.750 56 1.225 2.250
Notes
Min 0.0059
Inches Nom
Max 0.0394
0.425 7.800 9.100
0.0128 0.2992 0.3504
0.0262 0.0148 0.3031 0.3543 0.0295 56 0.0482 0.0886
0.0167 0.3071 0.3583
1.125 2.150
0.100 1.325 2.350
0.0443 0.0846
0.0039 0.0522 0.0925
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 2.
A1 Index Mark
256-Mbit, 79-Ball VF BGA Package Drawing and Dimensions
S1
D 1 2 3 4 5 6 7 8 9 10 11 12 13 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G
b e
A1 Index Mark
A B C D E F G
S2
E
Top View - Ball Side Down
Bottom View - Ball Side Up
A1
A2
A
Seating Plane
Y
Side View
Dimensions Table
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length (256Mb) Package Body Width (256Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Symbol A A1 A2 b D E e N Y S1 S2 Min 0.150 0.325 10.900 8.900 0.665 0.375 11.000 9.000 0.750 79 1.000 2.250 0.425 11.100 9.100 Millimeters Nom Max Notes 1.000
Drawing not to scale
Min 0.0059 0.0128 0.4291 0.3504
Inches Nom
Max 0.0394
0.0262 0.0148 0.4331 0.3543 0.0295 79 0.0394 0.0886
0.0167 0.4370 0.3583
0.900 2.150
0.100 1.100 2.350
0.0354 0.0846
0.0039 0.0433 0.0925
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
3.2
Figure 3.
SCSP Packages
128-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x10x1.2 mm)
8x10x1.2Q
A1 Index Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 21 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1
Top View - Ball Down
A2 A1
Bottom View - Ball U p
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
M in 0.200 0.325 9.900 7.900
M illimeters Nom M ax 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
M in 0.0079
Inches Nom
M ax 0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 4.
256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x11x1.0 mm)
A1 Index Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1
S1
S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Note: Dimensions A1, A2, and b are preliminary
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Symbol A A1 A2 b D E e N Y S1 S2 Min 0.117 0.300 10.900 7.900 0.740 0.350 11.00 8.00 0.80 88 1.200 1.100 0.400 11.100 8.100 Millimeters Nom Max 1.00 Notes Min 0.0046 0.0118 0.4291 0.3110 0.0291 0.0138 0.4331 0.3150 0.0315 88 0.0472 0.0433 0.0157 0.4370 0.3189 Inches Nom Max 0.0394
1.100 1.000
0.100 1.300 1.200
0.0433 0.0394
0.0039 0.0512 0.0472
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
4.0
4.1
Ballout and Signal Descriptions
Signal Ballout
This section includes signal ballouts for the following packages:
* VF BGA Package Ballout * SCSP Package Ballout 4.1.1 VF BGA Package Ballout
The Intel StrataFlash(R) Wireless Memory (L18) is available in a VF BGA package with 0.75 mm ball-pitch. Figure 5 shows the ballout for the 64-Mbit and 128-Mbit devices in the 56-ball VF BGA package with a 7x8 active-ball matrix. Figure 6 shows the device ballout for the 256-Mbit device in the 63-ball VF BGA package with a 7x9 active-ball matrix. Both package densities are ideal for space-constrained board applications Figure 5. 7x8 Active-Ball Matrix for 64-, and 128-Mbit Densities in VF BGA Packages
1 A A11 B A12 C A13 D A15 E VCCQ F VSS G D7
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1 A
A8
VSS
VCC
VPP
A18
A6
A4
A4
A6
A18
VPP
VCC
VSS
A8
A11 B
A9
A20
CLK
RST#
A17
A5
A3
A3
A5
A17
RST#
CLK
A20
A9
A12 C
A10
A21
ADV#
WE#
A19
A7
A2
A2
A7
A19
WE#
ADV#
A21
A10
A13 D
A14
WAIT
A16
D12
WP#
A22
A1
A1
A22
WP#
D12
A16
WAIT
A14
A15 E
D15
D6
D4
D2
D1
CE#
A0
A0
CE#
D1
D2
D4
D6
D15
VCCQ F
D14
D13
D11
D10
D9
D0
OE#
OE#
D0
D9
D10
D11
D13
D14
VSS G
VSSQ
D5
VCC
D3
VCCQ
D8
VSSQ
VSSQ
D8
VCCQ
D3
VCC
D5
VSSQ
D7
VFBGA 7x8 Top View - Ball Side Down
VFBGA 7x8 Bottom View - Ball Side Up
Note:
On lower-density devices, upper-address balls can be treated as NC. (e.g., for 64-Mbit density, A22 will be NC)
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 6.
1 2 3
7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package
4 5 6 7 8 9 10 11 12 13 13 12 11 10 9 8 7 6 5 4 3 2 1
A DU B DU C A13 D A15 E VCCQ F DU G DU DU D7 VSSQ D5 VCC D3 VCCQ Top View D8 VSSQ RFU DU DU DU DU RFU VSSQ D8 VCCQ D3 VCC D5 VSSQ D7 DU DU DU VSS D14 D13 D11 D10 D9 D0 OE# RFU DU DU DU DU RFU OE# D0 D9 D10 D11 D13 D14 VSS DU DU D15 D6 D4 D2 D1 CE# A0 A23 A23 A0 CE# D1 D2 D4 D6 D15 VCCQ A14 WAIT A16 D12 WP# A22 A1 A24 A24 A1 A22 WP# D12 A16 WAIT A14 A15 A10 A21 ADV# WE# A19 A7 A2 A25 A25 A2 A7 A19 WE# ADV# A21 A10 A13 DU A12 A9 A20 CLK RST# A17 A5 A3 RFU DU DU DU DU RFU A3 A5 A17 RST# CLK A20 A9 A12 DU DU DU A11 A8 VSS VCC VPP A18 A6 A4 RFU DU DU DU DU RFU A4 A6 A18 VPP VCC VSS A8 A11 DU DU
A
B
C
D
E
F
G
Ball Side Down-
Bottom View
Ball Side Up
Note:
On lower density devices upper address balls can be treated as RFUs. (A24 is for 512-Mbit and A25 is for 1-Gbit densities). All ball locations are populated.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 17
Intel StrataFlash(R) Wireless Memory (L18)
4.1.2
SCSP Package Ballout
The L18 wireless memory in QUAD+ ballout device is available in an 88-ball (80-active ball) Stacked Chip Scale Package (SCSP) for the 128- and 256-Mbit devices. For Mechanical Information, refer to Section 3.0, "Package Information" on page 12.
Figure 7.
88-Ball (80-Active Ball) SCSP Package Ballout
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
B
A4 A18 A1 9 V SS F1 -V CC F 2 -V C C A2 1 A11
C
A5 R-LB# A2 3 V SS S -C S 2 C LK A2 2 A12
D
A3 A17 A2 4 F -V P P , F -V P E N R -W E # P 1 -CS # A9 A13
E
A2 A7 A2 5 F-W P # A DV # A20 A1 0 A15
F
A1 A6 R -U B # F -R S T# F- W E # A8 A1 4 A16
G
A0 D8 D2 D10 D5 D13 W AIT F 2 - CE #
H
R -O E # D0 D1 D3 D1 2 D14 D7 F2 - O E #
J
S -C S 1 # F1 -O E # D9 D11 D4 D6 D1 5 V C CQ
K
F1 -C E # P 2 -C S # F3 -C E # S -V C C P -V C C F 2 -V C C V CC Q P - M o de
L
VSS VS S DU V CC Q F 1 -V C C VSS VSS VS S DU VSS DU
M
DU
T o p V ie w - B a ll S i d e D o w n Legend: G lo b a l S R A M / P S R A M s p e c if ic F la s h s p e c ific
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
4.2
Signal Descriptions
This section includes signal descriptions for the following packages:
* VF BGA Package Signal Descriptions * SCSP Package Signal Descriptions 4.2.1 VF BGA Package Signal Descriptions
Table 1 describes the active signals used on the Intel StrataFlash(R) Wireless Memory (L18), VF BGA package. Table 1.
Symbol A[MAX:0] DQ[15:0]
Signal Descriptions (Sheet 1 of 2)
Type Input Input/ Output Name and Function ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the CE# or OE# are deasserted. Data is internally latched during writes. ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low. CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it in standby, with DQ[15:0] and WAIT in High-Z. CLOCK: Synchronizes the device with the system's bus frequency in synchronous-read mode and increments the internal address generator. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. OUTPUT ENABLE: Active-low input. OE#-low enables the device's output data buffers during read cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z. RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. RST#-high enables normal operation. Exit from reset places the device in asynchronous read array mode. WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT's active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH. * In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous page mode, and all write modes, WAIT is deasserted. WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on the rising edge of WE#. WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted.
ADV#
Input
CE#
Input
CLK
Input
OE#
Input
RST#
Input
WAIT
Output
WE#
Input
WP#
Input
VPP
Power /lnput
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above VPPLmin to perform in-system program or erase. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may derate flash performance/behavior.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 19
Intel StrataFlash(R) Wireless Memory (L18)
Table 1.
Symbol VCC VCCQ VSS VSSQ DU RFU
Signal Descriptions (Sheet 2 of 2)
Type Power Power Power Power -- -- Name and Function Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO. Operations at invalid VCC voltages should not be attempted. Output Power Supply: Output-driver source voltage. This ball can be tied directly to VCC if operating within VCC range. Ground: Ground reference for device logic voltages. Connect to system ground. Ground: Ground reference for device output voltages. Connect to system ground. Do Not Use: Do not use this ball. This ball should not be connected to any power supplies, signals or other balls, and must be left floating. Reserved for Future Use: Reserved by Intel for future device functionality and enhancement.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
4.2.2
128/0 and 256/0 SCSP Package Signal Descriptions
Table 2 describes the active signals used on the 128/0 and 256/0 SCSP.
Table 2.
Symbol
Device Signal Descriptions for SCSP (Sheet 1 of 2)
Type Description ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
A[Max:0]
Input
* 128-Mbit Die: A[Max] = A22 * 256-Mbit Die: A[Max] = A23 DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data is internally latched during writes. FLASH CHIP ENABLE: Low-true: selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. F1-CE# selects the flash die. F2-CE# and F3-CE# are available on stacked combinations with two or three flash dies else they are RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility. SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. Treat this signal as NC (No Connect) for this device. PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. Treat this signal as NC (No Connect) for this device. FLASH OUTPUT ENABLE: Low-true; enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z.
DQ[15:0]
Input/ Output
F1-CE# F2-CE# F3-CE# Input
S-CS1# S-CS2
Input
P-CS#
Input
F1-OE# F2-OE#
Input
F1-OE# controls the outputs of the flash die. F2-OE# is available on stacked combinations with two or three flash dies else it is RFU. It can be pulled high to VCCQ through a 10K-ohm resistor for future design flexibility.
R-OE#
Input
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output buffers. R-OE#-high disables the RAM output buffers, and places the selected RAM outputs in High-Z. Treat this signal as NC (No Connect) for this device. FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die. Treat this signal as NC (No Connect) for this device. FLASH CLOCK: Synchronizes the device with the system's bus frequency in synchronous-read mode and increments the internal address generator. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT's active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH. * In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and valid data when deasserted. * In asynchronous page mode, and all write modes, WAIT is deasserted.
WE# R-WE#
Input Input
CLK
Input
WAIT
Output
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 21
Intel StrataFlash(R) Wireless Memory (L18)
Table 2.
WP#
Device Signal Descriptions for SCSP (Sheet 2 of 2)
Input FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the selected flash die. WP#-low enables the lock-down mechanism - locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. FLASH ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. In asynchronous mode, the address is latched when ADV# going high or continuously flows through if ADV# is held low.
ADV#
Input
R-UB# R-LB# RST#
Input
RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high order bytes on DQ[15:8], and R-LB#-low enables the RAM low-order bytes on DQ[7:0]. Treat this signal as NC (No Connect) for this device. FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. PSRAM MODE: Low-true; P-MODE is used to program the configuration register, and enter/exit low power mode. Treat this signal as NC (No Connect) for this device. Flash Program/Erase Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted.
Input
P-Mode
Input
VPP, VPEN
Power/ Input
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPPLmin. VPP must remain above VPPLmin to perform in-system flash modification. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 9 V may reduce block cycling capability. VPEN (Erase/Program/Block Lock Enables) is not available for L18 products. Flash Logic Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2. Write operations are inhibited when VCC VLKO. Device operations at invalid VCC voltages should not be attempted. SRAM Power Supply: Supplies power for SRAM operations. Treat this signal as NC (No Connect) for this device. PSRAM Power Supply: Supplies power for PSRAM operations. Treat this signal as NC (No Connect) for this device. Flash I/O Power: Supply power for the input and output buffers. Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserve for future device functionality/ enhancements. Contact Intel regarding their future use. Do Not Use: Do not connect to any other signal, or power supply; must be left floating. No Connect: No internal connection; can be driven or floated.
F1-VCC F2-VCC S-VCC P-VCC VCCQ VSS RFU DU NC
Power
Power Power Power Power -- -- --
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
4.3
Memory Map
See Table 3 and Table 4. The memory array is divided into multiple partitions; one parameter partition and several main partitions:
* 64-Mbit device. This contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit
main partitions.
* 128-Mbit device. This contains sixteen partitions: one 8-Mbit parameter partition, fifteen 8Mbit main partitions.
* 256-Mbit device. This contains sixteen partitions: one 16-Mbit parameter partition, fifteen 16Mbit main partitions. Table 3. Top Parameter Memory Map
Size (KW) 8-Mbit Parameter Partition 16 16 16 16 64 ... 64 Seven Partitions 64 ... Blk
43
64-Mbit 8-Mbit Parameter Partition 3FC000-3FFFFF 3F8000-3FBFFF 3F4000-3F7FFF 3F0000-3F3FFF 3E0000-3EFFFF ... 380000-38FFFF 370000-37FFFF ...
Size (KW) 16 16 16 16 64 ... 64 Fifteen Partitions 64 ...
Blk 130 129 128 127 126 ... 120 119
128-Mbit 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 780000-78FFFF 770000-77FFFF ... 000000-00FFFF
One Partition
56 55 ...
8-Mbit Main Partition
64
0
000000-00FFFF
8-Mbit Main Partitions
One Partition
66 65 64 63 62 ...
64
0
Size (KW) 16-Mbit Parameter Partition 16 16 16 16 64 ... 64 Seven Partitions 64 ...
Blk 258 257 256 255 254 ...
256-Mbit FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF ... 800000-80FFFF 000000-00FFFF
One Partition
240 F00000-FFFFFF 239 EF0000-EFFFFF
16-Mbit Main Partitions
64 64 ... 64
128
Eight Partitions
127 7F0000-7FFFFF
0
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 23
Intel StrataFlash(R) Wireless Memory (L18)
Table 4.
Bottom Parameter Memory Map
Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit
8-Mbit Main Partitions
Seven Partitions
Fifteen Partitions
64 ...
66 ...
3F0000-3FFFFF ...
8-Mbit Main Partitions
64 ...
130 7F0000-7FFFFF ... ... 080000-08FFFF 070000-07FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF ...
64 64
11 10 ... 4 3 2 1 0
080000-08FFFF 070000-07FFFF
64 64
11 10 ... 4 3 2 1 0
8-Mbit Parameter Partition
8-Mbit Parameter Partition
...
...
One Partition
64 16 16 16 16
010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
One Partition
64 16 16 16 16
Size (KW) Blk
256-Mbit
16-Mbit Main Partitions
Eight Partitions
64 ...
258 FF0000-FFFFFF ... ...
64 64 ...
131 800000-80FFFF 130 7F0000-7FFFFF ... ...
Seven Partitions
64 64
19 18 ... 4 3 2 1 0
100000-10FFFF 0F0000-0FFFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF ...
16-Mbit Parameter Partition
One Partition
64 16 16 16 16
April 2005 24
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
...
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
5.0
5.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
Parameter Temperature under bias Storage temperature Voltage on any signal (except VCC, VPP) VPP voltage VCC voltage VCCQ voltage Output short circuit current Maximum Rating -25 C to +85 C -65 C to +125 C -0.5 V to +2.5 V -0.2 V to +10 V -0.2 V to +2.5 V -0.2 V to +2.5 V 100 mA 1 1,2,3 1 1 4 Notes
Notes: 1. Voltages shown are specified with respect to VSS. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on VCC is VCC +0.5 V, which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ +0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods < 20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 3. Program/erase voltage is typically 1.7 V - 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 4. Output shorted for no more than one second. No more than one output shorted at a time.
5.2
Warning:
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Symbol TC VCC VCCQ VPPL VPPH tPPH Block Erase Cycles Operating Temperature VCC Supply Voltage I/O Supply Voltage VPP Voltage Supply (Logic Level) Factory word programming VPP Maximum VPP Hours Main and Parameter Blocks Main Blocks Parameter Blocks VPP = VPPH VPP = VCC VPP = VPPH VPP = VPPH 1.8 V Range 1.8 V Extended Range Parameter Min -25 1.7 1.7 1.35 0.9 8.5 100,000 Max +85 2.0 2.0 2.0 2.0 9.5 80 1000 2500 Cycles Hours 2 V Units C Notes 1
Notes: 1. TC = Case temperature 2. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V - 9.5 V for 1000 cycles on main blocks and 2500 cycles on parameter blocks.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 25
Intel StrataFlash(R) Wireless Memory (L18)
6.0
6.1
Sym
Electrical Specifications
DC Current Characteristics
Parameter VCCQ 1.7 V - 2.0 V 1.35 V - 2.0 V Unit Typ Max 1 VCC = VCCMax A VCCQ = VCCQMax VIN = VCCQ or VSS VCC = VCCMax A VCCQ = VCCQMax VIN = VCCQ or VSS VCC = VCCMax VCCQ = VCCQMax CE# = VCCQ A RST# = VCCQ (for ICCS) RST# = GND (for ICCD) WP# = VIH VCC = VCCMax VCCQ = VCCQMax CE# = VSSQ A RST# = V CCQ All inputs are at rail to rail (VCCQ or VSSQ). mA mA 4-Word Read mA Burst length = 4 VCC = VCCMax mA Burst length = 8 CE# = VIL mA Burst length = 16 OE# = VIH 1 Burst length = Inputs: VIL or mA Continuous VIH mA Burst length = 4 mA Burst length = 8 mA Burst length = 16 Burst Length = mA Continuous VPP = VPPL, program/erase in 1,3,4, mA progress 7 VPP = VPPH, program/erase in 1,3,5, mA progress 7 A CE# = VCCQ; suspend in progress 1,6,3 Test Conditions Notes
ILI
Input Load Current Output Leakage Current
-
1
ILO
DQ[15:0], WAIT 64-Mbit 128-Mbit 256-Mbit 64-Mbit 128-Mbit
15 20 25 15 20 25
1 30 70 110 30 70 110
ICCS ICCD
VCC Standby, Power Down
1,2
ICCAPS APS 256-Mbit Asynchronous Single-Word f = 5MHz (1 CLK) Page-Mode Read f = 13 MHz (5 CLK)
13 8 12 14 16 20 15 18 21 22
15 9 16 18 20 25 18 22 25 27 50 32 30 70 110 5
ICCR
Synchronous Burst Read Average VCC Read f = 40MHz, LC = 3 Current
Synchronous Burst Read f = 54MHz, LC = 4
ICCW, VCC Program Current, ICCE VCC Erase Current ICCWS, VCC Program Suspend Current, ICCES VCC Erase Suspend Current IPPS, VPP Standby Current, IPPWS, VPP Program Suspend Current, IPPES VPP Erase Suspend Current 64-Mbit 128-Mbit 256-Mbit
35 25 15 20 25 0.2
A VPP = VPPL, suspend in progress
1,3
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Sym IPPR IPPW IPPE Notes: 1. 2. 3. 4. 5. 6. 7. VPP Read
Parameter
VCCQ
1.7 V - 2.0 V 1.35 V - 2.0 V Unit Typ 2 0.05 8 0.05 8 Max 15 0.10 22 0.10 22
Test Conditions
Notes
VPP Program Current VPP Erase Current
A VPP VCC V = VPPL, program in progress mA PP VPP = VPPH, program in progress V = VPPL, erase in progress mA PP VPP = VPPH, erase in progress
1,3
All currents are RMS unless noted. Typical values at typical VCC, TC = +25C. ICCS is the average current measured over any 5 ms time interval 5 s after CE# is deasserted. Sampled, not 100% tested. VCC read + program current is the sum of VCC read and VCC program currents. VCC read + erase current is the sum of VCC read and VCC erase currents. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR ICCW, ICCE measured over typical or max times specified in Section 7.7, "Program and Erase Characteristics" on page 41
6.2
Sym VIL VIH VOL
DC Voltage Characteristics
VCCQ Parameter Min Input Low Voltage Input High Voltage Output Low Voltage 0 VCCQ - 0.2 Max 0.2 VCCQ 0.1 Min 0 VCCQ - 0.4 Max 0.4 VCCQ 0.1 V V V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VCCQ = VCCQMin IOH = -100 A 2 1 1 1.35 V - 2.0 V 1.7 V - 2.0 V Unit Test Condition Notes
VOH
Output High Voltage
VCCQ - 0.1 1.0 0.9
0.4 -
VCCQ - 0.1 1.0 0.9
0.4 -
V V V V
VPPLK VPP Lock-Out Voltage VLKO VCC Lock Voltage VLKOQ VCCQ Lock Voltage
NOTES: 1. VIL can undershoot to -0.4 V and VIH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less. 2. VPP VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 27
Intel StrataFlash(R) Wireless Memory (L18)
7.0
7.1
Figure 8.
AC Characteristics
AC Test Conditions
AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0V
Note:
Test Points
VCCQ/2 Output
IO_REF.WMF
AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Figure 9.
Transient Equivalent Testing Load Circuit
Device Under Test
CL
Out
Notes: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance.
Table 5.
Test configuration component value for worst case speed conditions
Test Configuration 1.35 V Standard Test 1.7 V Standard Test CL (pF) 30 30
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 10.
Clock Input AC Waveform
R201
CLK [C]
VIH VIL R202 R203
CLKINPUT.WMF
7.2
Table 6.
Capacitance
Capacitance
Symbol CIN Parameter Input Capacitance Signals Min 2 Typ 6 Max 7 Unit pF pF Condition Typ temp= 25 C, Max temp = 85 C, VCC=VCCQ=(0-1.95) V, Silicon die Note Address, CE#, WE#, OE#, RST#, CLK, ADV#, WP# Output Capacitance Data, WAIT
1,2
COUT 2 4 5 NOTES: 1. Sampled, not 100% tested. 2. Silicon die capacitance only, add 1 pF for discrete packages.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 29
Intel StrataFlash(R) Wireless Memory (L18)
7.3
Num
AC Read Specifications (VCCQ = 1.35 V - 2.0 V)
Symbol Parameter All DensitiesSpeed Min -90 Max 90 90 25 150 20 20 17 17 17 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1,3 1 1,3 1,3 1,3 1,2 1 1,3 1,2,3 6 Units Notes
Asynchronous Specifications
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R15 R16 R17 tAVAV Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# low to WAIT valid OE# low to WAIT in low-Z OE# high to WAIT in high-Z 90 0 0 0 17 0 -
tAVQV tELQV tGLQV
tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGLTV
tGLTX tGHTZ
Latching Specifications
R101 R102 R103 R104 R105 R106 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA tphvh Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high Page address access RST# high to ADV# high 7 10 7 7 7 30 90 30 ns ns ns ns ns ns ns ns 1,4 1 1 1
Clock Specifications
R200 R201 R202 R203 fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time 21.3 4.5 47 3 MHz ns ns ns 1,3
Synchronous Specifications
R301 R302 R303 R304 R305 R306 R307 R311 R312 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV tCHQX tCHAX tCHTV tCHVL tCHTX Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid Output hold from CLK Address hold from CLK CLK to WAIT valid CLK Valid to ADV# Setup WAIT Hold from CLK 7 7 7 3 7 0 3 17 17 ns ns ns ns ns ns ns ns ns 1,5 1,4,5 1,5 1 1,5 1
NOTES: 1. See Figure 8, "AC Input/Output Reference Waveform" on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in this table will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
7.4
AC Read Specifications for 64-Mbit and 128-Mbit Densities (VCCQ = 1.7 V - 2.0 V)
Symbol Parameter Speed Min -85 Max 85 85 20 150 17 17 14 14 14 17 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1,3 1 1,3 1,3 1,3 1,2 1 1,3 1,2,3 6 Units Notes
Num
Asynchronous Specifications
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R15 R16 R17 tAVAV Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# low to WAIT valid OE# low to WAIT in low-Z OE# high to WAIT in high-Z 85 0 0 0 14 0 -
tAVQV tELQV tGLQV
tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGLTV
tGLTX tGHTZ
Latching Specifications
R101 R102 R103 R104 R105 R106 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA tphvh fCLK tCLK tCH/CL tFCLK/RCLK Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high Page address access RST# high to ADV# high 7 10 7 7 7 30 85 25 ns ns ns ns ns ns ns ns 1 1,6 1 1,4 1 1
Clock Specifications
R200 R201 R202 R203 CLK frequency CLK period CLK high/low time CLK fall/rise time 18.5 3.5 54 3 MHz ns ns ns 1,3
Synchronous Specifications
R301 R302 R303 R304 R305 R306 R307 R311 R312 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV tCHQX tCHAX tCHTV tCHVL tCHTX Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid Output hold from CLK Address hold from CLK CLK to WAIT valid CLK Valid to ADV# Setup WAIT Hold from CLK 7 7 7 3 7 0 3 14 14 ns ns ns ns ns ns ns ns ns 1,5 1,4,5 1,5 1 1,5 1
NOTES: 1. See Figure 8, "AC Input/Output Reference Waveform" on page 28 for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 31
Intel StrataFlash(R) Wireless Memory (L18)
7.5
AC Read Specifications for 256-Mbit Density (VCCQ = 1.7 V - 2.0 V)
Symbol Parameter Speed Min -85 Max 85 88 85 88 20 150 17 17 14 14 14 17 Units Notes
Num
Asynchronous Specifications
R1 tAVAV Read cycle time
VCC = VCCQ = 1.8 V - 2.0 V VCC = VCCQ = 1.7 V - 2.0 V VCC = VCCQ = 1.8 V - 2.0 V VCC = VCCQ = 1.7 V - 2.0 V VCC = VCCQ = 1.8 V - 2.0 V VCC = VCCQ = 1.7 V - 2.0 V
85 88 0 0 0 14 0 -
ns
R2
tAVQV tELQV tGLQV
tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGLTV
tGLTX tGHTZ
Address to output valid
ns
6
R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R15 R16 R17
CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z
ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1,3 1 1,3 1,3 1,3 1,2 1 1,3 1,2,3
Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# low to WAIT valid OE# low to WAIT in low-Z OE# high to WAIT in high-Z
Latching Specifications
R101 R102 R103 R104 R105 R106 R108 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA tphvh fCLK tCLK tCH/CL tFCLK/RCLK Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high Page address access RST# high to ADV# high 7 10 85 88 25 ns ns ns ns ns ns ns ns 1 1,6 1 1,4 1 1
VCC = VCCQ = 1.8 V - 2.0 VCC = VCCQ = 1.7 V - 2.0
7 7 7 30
Clock Specifications
R200 R201 R202 R203 CLK frequency CLK period CLK high/low time CLK fall/rise time 18.5 3.5 54 3 MHz ns ns ns 1,3
Synchronous Specifications
R301 R302 R303 R304 R305 R306 R307 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV tCHQX tCHAX tCHTV Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid Output hold from CLK Address hold from CLK CLK to WAIT valid 7 7 7 3 7 14 14 ns ns ns ns ns ns ns 1,5 1,4,5 1,5 1
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Num R311 R312
Symbol tCHVL tCHTX
Parameter CLK Valid to ADV# Setup WAIT Hold from CLK
Speed Min 0 3
-85 Max -
Units ns ns
Notes 1 1,5
NOTES: 1. See Figure 8, "AC Input/Output Reference Waveform" on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
Figure 11.
Asynchronous Single-Word Read with ADV# Low
R1 R2
Address [A] ADV# R3 CE# [E} R4 OE# [G] R15 WAIT [T] R7 R6 Data [D/Q] R5 RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
R8
R9
R17
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 33
Intel StrataFlash(R) Wireless Memory (L18)
Figure 12.
Asynchronous Single-Word Read with ADV# Latch
R1 R2
Address [A] A[1:0][A] R101 R105 ADV# R3 CE# [E} R4 OE# [G] R15 WAIT [T] R7 R6 Data [D/Q] R10 R17 R9 R8 R106
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
Figure 13.
Asynchronous Page-Mode Read Timing
R1 R2
A[Max:2] [A] A[1:0] R101 R105 ADV# R3 CE# [E] R4 OE# [G] R15 WAIT [T] R7 DATA [D/Q] R108 R9 R17 R10 R8
R106
Note:
WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 14.
Synchronous Single-Word Array or Non-array Read Timing
R301 R306
CLK [C] R2 Address [A] R101 R105 R104 ADV# [V] R303 R102 R3 CE# [E] R7 OE# [G] R15 WAIT [T] R4 R304 Data [D/Q] R305 R307 R312 R17 R9 R8 R106
Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst.
Figure 15.
Continuous Burst Read, showing an Output Delay Timing
R301 R302 R306 R304 R304 R304
CLK [C] R2 R101 Address [A] R106 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R304 R4 R7 Data [D/Q] R305 R305 R305 R305 R307 R312
Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low). 2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 35
Intel StrataFlash(R) Wireless Memory (L18)
Figure 16.
Synchronous Burst-Mode Four-Word Read Timing
Latency Count R302 R301 R306
CLK [C] R2 Address [A] R101 A R105 R102 ADV# [V] R303 R3 CE# [E] R9 OE# [G] R15 WAIT [T] R4 R7 Data [D/Q] R304 R304 R305 Q0 R307 R17 R8 R106
R10 Q1 Q2 Q3
Note:
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
Figure 17.
Burst Suspend Timing
R304 CLK
R305
R305
R1 R2 Address [A] R101 R105 ADV# R3 CE# [E] R4 OE# [G] R15 WAIT [T] WE# [W] R7 R6 DATA [D/Q] Q0 R304 Q1 Q1 R304 Q2 R17 R15 R312 R9 R4
R106
Notes: 1. CLK can be stopped in either high or low state. 2. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
7.6
AC Write Specifications
Nbr. Symbol Parameter (1, 2) Min Max Units Notes
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W16 W18 W19 W20 W21 W22 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL tWHQV tWHAV
RST# high recovery to WE# low CE# setup to WE# low WE# write pulse width low Data setup to WE# high Address setup to WE# high CE# hold from WE# high Data hold from WE# high Address hold from WE# high WE# pulse width high VPP setup to WE# high VPP hold from Status read WP# hold from Status read WP# setup to WE# high WE# high to OE# low WE# high to read valid WE# high to Address valid
150 0 50 50 50 0 0 0 20 200 0 0 200 0 tAVQV + 35 0 19 19 -
20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1,2,3 1,2,3 1,2,4
1,2
1,2,5 1,2,3,7 1,2,3,7 1,2,9 1,2,3,6,10 1,2,3,6
Write to Asynchronous Read Specifications Write to Synchronous Read Specifications tWHCH/L WE# high to Clock valid tWHVH tVHWL tCHWL WE# high to ADV# high ADV# high to WE# low Clock high to WE# low 1,2,3,6,10
Write Specifications with Clock Active 1,2,3,11
Write timing characteristics during erase suspend are the same as write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL). tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read. VPP and WP# should be at a valid level until erase or program success is determined. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and W20 for synchronous read. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 37
Intel StrataFlash(R) Wireless Memory (L18)
Figure 18.
Write to Write Timing
W5 W8 W5 W8
Address [A] W2 CE# [E} W3 WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] W7 W4 W7 W9 W3 W6 W2 W6
Figure 19.
Asynchronous Read to Write Timing
R1 R2 W5 W8
Address [A] R3 CE# [E} R4 OE# [G] W2 WE# [W] R15 WAIT [T] R7 R6 Data [D/Q] R5 RST# [P] Q R10 W4 D W7 R17 W3 W6 R9 R8
Note:
Wait deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 20.
Write to Asynchronous Read Timing
W5 W8 R1
Address [A] ADV# [V] W2 CE# [E} W3 WE# [W] W14 OE# [G] R15 WAIT [T] R4 W4 Data [D/Q] W1 RST# [P] D W7 R2 R3 Q R8 R9 R17 W18 W6 R10
Figure 21.
Synchronous Read to Write Timing
Latency C ount R 301 R 302 R 306
CLK [C ] R2 R101 Address [ A] R 105 R 102 ADV# [ V] R 303 R3 CE# [E] R4 R8 OE# [G] W 21 W 22 W2 W E# R16 W AIT [T] R 304 R7 Data [D/Q] Q R305 D W7 D R 307 R312 W8 W3 W9 W 21 W 22 W 15 R 11 R13 W6 R106 R 104 W5 W 18
Note:
WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait asserted low). Clock is ignored during write operation.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 39
Intel StrataFlash(R) Wireless Memory (L18)
Figure 22.
Write to Synchronous Read Timing
Latency Count R302 R301 R2
CLK W5 Address [A] R106 R104 ADV# W6 W2 CE# [E} W18 W19 W20 R11 R303 W8 R306
W3 WE# [W]
R4 OE# [G] R15 WAIT [T] W7 W4 Data [D/Q] W1 RST# [P] D R3 Q R304 R305 R304 Q R307
Note:
WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0 Wait asserted low).
April 2005 40
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
7.7
Program and Erase Characteristics
Nbr. Symbol Parameter Min Conventional Word Programming Single word Program W200 tPROG/W Time Single cell Buffered Programming W200 tPROG/W Program Single word One Buffer (32 words) W201 tPROG/PB Time Buffered Enhanced Factory Programming W451 tBEFP/W Single word Program t Buffered EFP Setup W452 BEFP/
Setup
VPPL Typ 90 30 90 440 n/a n/a 0.4 1.2 20 20 Max 180 60 180 880 n/a n/a 2.5 4 25 25 Min 5 -
VPPH Typ 85 30 85 340 10 0.4 1.0 20 20 Max 170 60 170 680 2.5 4 25 25
Units Notes
n/a n/a -
s
1
s
1
1,2 s 1
Erasing and Suspending W500 tERS/PB Erase Time W501 tERS/MB W600 tSUSP/P Suspend Latency W601 tSUSP/E
16-Kword Parameter 64-Kword Main Program suspend Erase suspend
s 1 s
Notes: 1. Typical values measured at TC = +25 C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
April 2005 41
Intel StrataFlash(R) Wireless Memory (L18)
8.0
8.1
Power and Reset Specifications
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active-low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. System designers should guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting either signal inhibits writes to the device. The Command User Interface (CUI) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see Section 9.2, "Device Commands" on page 47).
Nbr. Symbol P1 P2 tPLPH tPLRH Parameter RST# pulse width low RST# low to device reset during erase RST# low to device reset during program VCC Power valid to RST# deassertion (high) Min 100 60 Max 25 25 Unit ns Notes 1,2,3,4 1,3,4,7 1,3,4,7 1,4,5,6
s P3 tVCCPH Notes: 1. These specifications are valid for all device versions (packages and speeds). 2. The device may reset if tPLPH is < tPLPHmin, but this is not guaranteed. 3. Not applicable if RST# is tied to Vcc. 4. Sampled, but not 100% tested. 5. If RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC VCC min. 6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC VCC(min). 7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 23.
Reset Operation Waveforms
P1 R5
(A) Reset during read mode
RST# [P]
VIH VIL
P2
(B) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P2
(C) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P3
(D) VCC Power-up to RST# high
VCC
VCC 0V
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and correct decoupling capacitor selection suppress transient voltage peaks. Because Intel(R) Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 F ceramic capacitor connected to a corresponding ground connection. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 F electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
8.4
Automatic Power Saving
Automatic Power Saving (APS) provides low power operation during a read's active state. ICCAPS is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During APS, average current is measured over the same time interval 5 s after the following events happen: (1) there is no internal read, program or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS.
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides control of all insystem read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST#-high enable device read operations. The device internally decodes upper address inputs to determine the accessed partition. ADV#-low opens the internal address latches. OE#-low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high or continuously flows through if ADV# is held low. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL). Bus cycles to/from the L18 device conform to standard microprocessor bus operations. Table 7 summarizes the bus operations and the logic levels that must be applied to the device's control signal inputs.
Table 7.
Bus Operations Summary
RST# VIH VIH VIH VIH VIH VIH VIL CLK X Running Halted X X X X ADV# L L X L X X X CE# L L L L L H X OE# L L H H H X X WE# H H H L H X X WAIT Deasserted Driven High-Z High-Z High-Z High-Z High-Z DQ[15:0] Output Output Output Input High-Z High-Z High-Z 1 2 2 2,3 Notes
Bus Operation Asynchronous Read Synchronous Burst Suspend Write Output Disable Standby Reset
Notes: 1. Refer to the Table 8, "Command Bus Cycles" on page 47 for valid DQ[15:0] during a write operation. 2. X = Don't Care (H or L). 3. RST# must be at VSS 0.2 V to meet the maximum specified power-down current.
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, "Read Operations" on page 50 for details on the available read modes, and see Section 15.0, "Special Read States" on page 75 for details regarding the available read states. The Automatic Power Savings (APS) feature provides low power operation following reads during active mode. After data is read from the memory array and the address lines are quiescent, APS automatically places the device into standby. In APS, device current is reduced to ICCAPS (see Section 6.1, "DC Current Characteristics" on page 26).
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 8, "Command Bus Cycles" on page 47 shows the bus cycle sequence for each of the supported device commands, while Table 9, "Command Codes and Definitions" on page 48 describes each command. See Section 7.0, "AC Characteristics" on page 28 for signaltiming details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z.
9.1.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During standby, average current is measured over the same time interval 5 s after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed.
9.1.5
Reset
As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU.
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Intel StrataFlash(R) Wireless Memory (L18)
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state. Note: If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, "AC Characteristics" on page 28 for details about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 8, "Command Bus Cycles" on page 47. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internally-timed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command.
Table 8.
Mode
Command Bus Cycles (Sheet 1 of 2)
Command Read Array Read Device Identifier Bus Cycles 1 2 2 2 1 2 >2 >2 2 1 1 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 PnA PnA PnA PnA X WA WA WA BA X X BA BA BA Data2 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 0x20 0xB0 0xD0 0x60 0x60 0x60 Write Write Write BA BA BA 0x01 0xD0 0x2F Write Write Write Write WA WA WA BA WD N-1 0xD0 0xD0 Read Read Read PBA+IA ID Second Bus Cycle Oper Addr1 Data2
Read
CFI Query Read Status Register Clear Status Register Word Program
PnA+QA QD PnA SRD
Program
Buffered Program3 Buffered Enhanced Factory Program (Buffered EFP)4
Erase Suspend
Block Erase Program/Erase Suspend Program/Erase Resume
Block Locking/ Unlocking
Lock Block Unlock Block Lock-down Block
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Intel StrataFlash(R) Wireless Memory (L18)
Table 8.
Mode
Command Bus Cycles (Sheet 2 of 2)
Command Program Protection Register Bus Cycles 2 2 2 First Bus Cycle Oper Write Write Write Addr1 PRA LRA RCD Data2 0xC0 0xC0 0x60 Second Bus Cycle Oper Write Write Write Addr1 PRA LRA RCD Data2 PD LRD 0x03
Protection Program Lock Register Configuration Program Read Configuration Register
Notes: 1. First command cycle address should be the same as the operation's target address. PnA = Address within the partition. PBA = Partition base address. IA = Identification code address offset. QA = CFI Query address offset. BA = Address within the block. WA = Word address of memory location to be written. PRA = Protection Register address. LRA = Lock Register address. X = Any valid address within the device. 2. ID = Identifier data. QD = Query data on DQ[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. PD = Protection Register data. LRD = Lock Register data. RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition. 3. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data.
9.3
Command Definitions
Valid device command codes and descriptions are shown in Table 9.
Table 9.
Mode
Command Codes and Definitions (Sheet 1 of 2)
Code Device Mode 0xFF Read Array 0x70 Read Status Register Description Places the addressed partition in Read Array mode. Array data is output on DQ[15:0]. Places the addressed partition in Read Status Register mode. The partition enters this mode after a program or erase command is issued. Status Register data is output on DQ[7:0].
Read
Read Device Places the addressed partition in Read Device Identifier mode. Subsequent reads from ID or addresses within the partition outputs manufacturer/device codes, Configuration Register Configuration data, Block Lock status, or Protection Register data on DQ[15:0]. Register Places the addressed partition in Read Query mode. Subsequent reads from the partition 0x98 Read Query addresses output Common Flash Interface information on DQ[7:0]. Clear Status The WSM can only set Status Register error bits. The Clear Status Register command is 0x50 Register used to clear the SR error bits. 0x90
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Intel StrataFlash(R) Wireless Memory (L18)
Table 9.
Mode
Command Codes and Definitions (Sheet 2 of 2)
Code Device Mode Description First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the Word Program partition responds only to Read Status Register and Program Suspend commands. CE# Setup or OE# must be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array read. The Read Array command must be issued to read array data after programming has finished. Alternate Word Program Equivalent to the Word Program Setup command, 0x40. Setup Buffered This command loads a variable number of bytes up to the buffer size of 32 words onto the Program program buffer. Buffered The confirm command is Issued after the data streaming for writing into the buffer is done. Program This instructs the WSM to perform the Buffered Program algorithm, writing the data from Confirm the buffer to the flash memory array. Buffered First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode Enhanced (Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that Factory initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP Programming mode begins. Setup Buffered EFP If the previous command was Buffered EFP Setup (0x80), the CUI latches the address Confirm and data, and prepares the device for Buffered EFP mode. First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the block addressed by the Erase Confirm Block Erase command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets Setup Status Register bits SR[4] and SR[5], and places the addressed partition in read status register mode. If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During block-erase operations, the partition Block Erase responds only to Read Status Register and Erase Suspend commands. CE# or OE# must Confirm be toggled to update the Status Register in asynchronous read. CE# or ADV# must be toggled to update the Status Register Data for synchronous Non-array read. This command issued to any device address initiates a suspend of the currentlyProgram or executing program or block erase operation. The Status Register indicates successful Erase suspend operation by setting either SR[2] (program suspended) or SR[6] (erase Suspend suspended), along with SR[7] (ready). The Write State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). Suspend This command issued to any device address resumes the suspended program or blockResume erase operation. First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. Lock Block If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down Setup (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. Lock Block If the previous command was Block Lock Setup (0x60), the addressed block is locked. If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. Unlock Block If the addressed block is in a lock-down state, the operation has no effect. Lock-Down If the previous command was Block Lock Setup (0x60), the addressed block is locked Block down. Program First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock Protection Register program operation. The second cycle latches the register address and data, and Register starts the programming algorithm. Setup Read First cycle of a 2-cycle command; prepares the CUI for device read configuration. If the Configuration Set Read Configuration Register command (0x03) is not the next command, the CUI sets Register Status Register bits SR[4] and SR[5], indicating a command sequence error. Setup Read If the previous command was Read Configuration Register Setup (0x60), the CUI latches Configuration the address and writes A[15:0] to the Read Configuration Register. Following a Configure Register Read Configuration Register command, subsequent read operations access array data.
0x40
0x10 Write 0xE8 0xD0
0x80
0xD0
0x20 Erase 0xD0
0xB0 Suspend 0xD0
0x60 Block Locking/ 0x01 Unlocking 0xD0 0x2F
Protection
0xC0
0x60 Configuration 0x03
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Intel StrataFlash(R) Wireless Memory (L18)
10.0
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, "Read Configuration Register (RCR)" on page 51). Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read Array. To change a partition's read state, the appropriate read command must be written to the device (see Section 9.2, "Device Commands" on page 47). See Section 15.0, "Special Read States" on page 75 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail.
10.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, "Read Configuration Register (RCR)" on page 51). To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time tAVQV delay. (see Section 7.0, "AC Characteristics" on page 28). In asynchronous page mode, four data words are "sensed" simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the data buffer at any given time.
10.2
Synchronous Burst-Mode Read
Section 10.3, "Read Configuration Register (RCR)" on page 51continuous-wordsTo perform a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted.
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During synchronous array and non-array read modes, the first word is output from the data buffer on the next valid CLK edge after the initial access latency delay (see Section 10.3.2, "Latency Count" on page 52). Subsequent data is output on valid CLK edges following a minimum delay. However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. Figure 14Figure 16
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. The system processor can resume the burst sequence later. Burst suspend provides maximum benefit in non-cache systems. Burst accesses can be suspended during the initial access latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed without limit as long as device operation conditions are met. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. WAIT is in High-Z during OE# deassertion. To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK edges resume the burst sequence. Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is placed in high-impedance state when OE# is deasserted and resumed active when OE# is re-asserted. See Figure 17, "Burst Suspend Timing" on page 36.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 9.2, "Device Commands" on page 47). RCR contents can be examined using the Read Device Identifier command, and then reading from + 0x05 (see Section 15.2, "Read Device Identifier" on page 76). The RCR is shown in Table 10. The following sections describe each RCR bit.
Table 10.
Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read Mode RES Latency Count WAIT Polarity Data Hold WAIT Delay Burst Seq CLK Edge RES RES Burst Wrap Burst Length
RM 15 Bit
R 14 13
LC[2:0] 12 11
WP 10
DH 9
WD 8
BS 7
CE 6
R 5
R 4
BW 3 2
BL[2:0] 1 0
Name
Description
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
Table 10.
15 14
Read Configuration Register Description (Sheet 2 of 2)
Read Mode (RM) Reserved (R) Latency Count (LC[2:0]) 0 = Synchronous burst-mode read 1 = Asynchronous page-mode read (default) Reserved bits should be cleared (0) 010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7 (default) (Other bit settings are reserved) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 0 =WAIT deasserted with valid data 1 =WAIT deasserted one data cycle before valid data (default) 0 =Reserved 1 =Linear (default) 0 = Falling edge 1 = Rising edge (default) Reserved bits should be cleared (0) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 =No Wrap; Burst accesses do not wrap within burst length (default) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved)
13:11
10 9 8 7 6 5:4 3 2:0
Wait Polarity (WP) Data Hold (DH) Wait Delay (WD) Burst Sequence (BS) Clock Edge (CE) Reserved (R) Burst Wrap (BW) Burst Length (BL[2:0])
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) Wait must be deasserted with valid data (WD = 0). WD = 1 is not supported.
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 24 shows the data output latency for the different settings of LC[2:0]. Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however, a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states. Refer to Table 11 and Table 12 for Latency Code Settings.
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 24.
First-Access Latency Count
CLK [C]
Valid Address
Address [A]
ADV# [V] Code 0 (Reserved) DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q] DQ15-0 [D/Q]
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code 1
(Reserved
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
Code 2
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code 3
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code 4
Valid Output
Valid Output
Valid Output
Valid Output
Code 5
Valid Output
Valid Output
Valid Output
Code 6
Valid Output
Valid Output
Code 7
Valid Output
Table 11.
LC and Frequency Support (tAVQV/tCHQV = 85 ns / 14 ns)
VCCQ = 1.7 V to 2.0 V Latency Count Settings 2 3 4, 5, 6 or 7 Frequency Support (MHz) 28 40 54
Table 12.
LC and Frequency Support (tAVQV/tCHQV = 90 ns / 17 ns)
VCCQ = 1.35 V to 2.0 V Latency Count Settings 2 3, 4, 5, 6 or 7 Frequency Support (MHz) 27 40
See Figure 25, "Example Latency Count Setting" on page 54.
Datasheet
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 25.
Example Latency Count Setting
0 1 2 tData
3
4
CLK CE# ADV# A[MAX:0]
Code 3 Address
D[15:0]
High-Z
Data
R103
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted, RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode (RCR[15]=0). The WAIT signal is only "deasserted" when data is valid on the bus. When the device is operating in synchronous non-array read mode, such as read status, read ID, or read query the WAIT signal is also "deasserted" when data is valid on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. When the device is operating in asynchronous page mode, asynchronous single word read mode, and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure 12, "Asynchronous Single-Word Read with ADV# Latch" on page 34, and Figure 13, "Asynchronous Page-Mode Read Timing" on page 34.
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Intel StrataFlash(R) Wireless Memory (L18)
Table 13.
WAIT Functionality Table
Condition WAIT Notes
CE# = `1', OE# = `X' CE# = `X', OE# = `1' CE# ='0', OE# = `0' Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads All Writes
High-Z
1
Active Active Active Deasserted High-Z
1 1 1 1 1,2
Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts 2. When OE# = VIH during writes, WAIT = High-Z
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on DQ[15:0] for one or two-clock cycles. This period of time is called the "data cycle". When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 26). The processor's data setup time and the flash memory's clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) One CLK Period (ns) tDATA = Data set up to Clock (defined by CPU) For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming tCHQV = 20 ns and tDATA = 4ns. Applying these values to the formula above: 20 ns + 4 ns 25 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be used.
Datasheet
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 26.
Data Hold Timing
CLK [C]
1 CLK Data Hold 2 CLK Data Hold
Valid Output Valid Output Valid Output
D[15:0] [Q]
D[15:0] [Q]
Valid Output
Valid Output
10.3.5
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before invalid data is output on DQ[15:0]. When WD is set, WAIT is asserted one data cycle before invalid data (default). When WD is cleared, WAIT is asserted during invalid data.
10.3.6
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 14 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 14.
Burst Sequence Word Ordering (Sheet 1 of 2)
Start Addr. (DEC) 0 1 2 3 4 5 6 7 14 15 ... 0 1 2 3 4 5 6 7 ... Burst Addressing Sequence (DEC) Burst Wrap (RCR[3]) 0 0 0 0 0 0 0 0 0 0 ... 1 1 1 1 1 1 1 1 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 ... 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 4-Word Burst (BL[2:0] = 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-Word Burst (BL[2:0] = 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... ... 16-Word Burst (BL[2:0] = 0b011) 0-1-2-3-4...14-15 1-2-3-4-5...15-0 2-3-4-5-6...15-0-1 3-4-5-6-7...15-0-1-2 4-5-6-7-8...15-0-1-2-3 5-6-7-8-9...15-0-1-2-3-4 6-7-8-9-10...15-0-1-2-3-4-5 7-8-9-10...15-0-1-2-3-4-5-6 14-15-0-1-2...12-13 15-0-1-2-3...13-14 0-1-2-3-4...14-15 1-2-3-4-5...15-16 2-3-4-5-6...16-17 3-4-5-6-7...17-18 4-5-6-7-8...18-19 5-6-7-8-9...19-20 6-7-8-9-10...20-21 7-8-9-10-11...21-22 ... ... Continuous Burst (BL[2:0] = 0b111) 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ... ...
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Intel StrataFlash(R) Wireless Memory (L18)
Table 14.
Burst Sequence Word Ordering (Sheet 2 of 2)
14 15 ... ... 1 1 ... ... 14-15-16-17-18...28-29 15-16-17-18-19...29-30 ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ...
10.3.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
10.3.8
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence's start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn't occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 14, "Burst Sequence Word Ordering" on page 56). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the "burstable" address space.
Datasheet
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11.0
Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (Buffered EFP) (80h, D0h). See Section 9.0, "Device Operations" on page 45 for details on the various programming commands issued to the device. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, "Security Modes" on page 66 for details on locking and unlocking blocks. The following sections describe device programming in detail.
11.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, "Device Operations" on page 45). This is followed by a second write to the device with the address and data to be programmed. The partition accessed during both write cycles outputs Status Register data when read. The partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. See Figure 39, "Word Program Flowchart" on page 85. Programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes "ones" to "zeros." Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, "Erase Operations" on page 64). The Status Register can be examined for programming progress and errors by reading any address within the partition that is being programmed. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing programming progress to be monitored at that partition's address. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the programming partition during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort.
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Intel StrataFlash(R) Wireless Memory (L18)
Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed.
11.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, "Operating Conditions" on page 25 for limitations when VPP = VPPH.
Note:
When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 27, "Example VPP Supply Connections" on page 63 shows examples of device power supply configurations.
11.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, "Device Commands" on page 47), Status Register information is updated and reflects the availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 41, "Buffer Program Flowchart" on page 87). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. Reading from another partition is allowed while data is being programmed into the array from the write buffer (see Section 14.0, "Dual-Operation Considerations" on page 71).
Datasheet
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When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, "Operating Conditions" on page 25 for limitations when operating the device with VPP = VPPH). If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash programming for today's beat-rate-sensitive manufacturing environments. The enhanced programming algorithm used in Buffered EFP eliminates traditional programming elements that drive up overhead in device programmer systems. Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 42, "Buffered EFP Flowchart" on page 88). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device's write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered EFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM's internal verification to ensure that the device has programmed properly. This eliminates the external postprogram verification and its associated overhead.
11.3.1
Buffered EFP Requirements and Considerations
Buffered EFP requirements:
* * * * *
Ambient temperature: TA = 25C, 5C VCC within specified operating range. VPP driven to VPPH. Target block unlocked before issuing the Buffered EFP Setup and Confirm commands. The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired.
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Intel StrataFlash(R) Wireless Memory (L18)
* WA0 must align with the start of an array buffer boundary1.
Buffered EFP considerations:
* * * * *
For optimum performance, cycling must be limited below 100 erase cycles per block2. Buffered EFP programs one block at a time; all buffer data must fall within a single block3. Buffered EFP cannot be suspended. Programming to the flash memory array can occur only when the buffer is full4. Read operation while performing Buffered EFP is not supported.
NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
11.3.2
Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level.
Note:
Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer.
11.3.3
Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For Buffered EFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm will be aborted and the program fail (SR[4]) flag will be set.
Datasheet
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Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the Buffered EFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block's range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the Buffered EFP Exit phase.
11.3.4
Buffered EFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. When exiting the Buffered EFP algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. After Buffered EFP exit, any valid command can be issued to the device.
11.4
Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from memory locations other than the one being programmed. The Program Suspend command can be issued to any device address; the corresponding partition is not affected. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 40, "Program Suspend/Resume Flowchart" on page 86). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.7, "Program and Erase Characteristics" on page 41. To read data from blocks within the suspended partition, the Read Array command must be issued to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. A program operation does not need to be suspended in order to read data from a block in another partition that is not programming. If the other partition is already in a Read Array, Read Device Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read.
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Intel StrataFlash(R) Wireless Memory (L18)
During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset.
11.5
Program Resume
The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any partition. When read at the partition that's programming, the device outputs data corresponding to the partition's last state. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 40, "Program Suspend/Resume Flowchart" on page 86).
11.6
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK.
Figure 27.
Example VPP Supply Connections
VCC VPP
10K
VCC VPP
VCC
PROT #
VCC VPP
* Factory Programming with VPP = V PPH * Complete write/Erase Protection when VPP VPPLK
* Low-voltage Programming only * Logic Control of Device Protection
VCC VPP=VPPH
VCC VPP
VCC
VCC VPP
* Low Voltage and Factory Programming
* Low Voltage Programming Only * Full Device Protection Unavailable
Datasheet
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12.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail.
12.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, "Device Commands" on page 47). Next, the Block Erase Confirm command is written to the address of the block to be erased. Erasing can occur in only one partition at a time; all other partitions must be in a read state. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 43, "Block Erase Flowchart" on page 89). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes "zeros" to "ones." Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, "Programming Operations" on page 58). The Status Register can be examined for block erase progress and errors by reading any address within the partition that is being erased. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing erase progress to be monitored at that partition's address. SR[0] indicates whether the addressed partition or another partition is erasing. The partition's Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed.
12.2
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address; the corresponding partition is not affected. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 40, "Program Suspend/Resume Flowchart" on page 86).
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When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.7, "Program and Erase Characteristics" on page 41. To read data from blocks within the suspended partition (other than an erase-suspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. To read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. If the other partition is already in Read Array, Read Device Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset.
12.3
Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any partition. When read at the partition that's erasing, the device outputs data corresponding to the partition's last state. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 40, "Program Suspend/Resume Flowchart" on page 86).
12.4
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.
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13.0
Security Modes
The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail.
13.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 11.6, "Program Protection" on page 63 and Section 12.4, "Erase Protection" on page 65).
13.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block's address (see Section 9.2, "Device Commands" on page 47 and Figure 45, "Block Lock Operations Flowchart" on page 91). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is below VPPLK.
13.1.2
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 9.2, "Device Commands" on page 47). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 28, "Block Locking State Diagram" on page 67).
13.1.3
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, "Device Commands" on page 47). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to lockeddown state, a Lock-Down command must be issued prior to changing WP# to VIL. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 28, "Block Locking State Diagram" on page 67).
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Intel StrataFlash(R) Wireless Memory (L18)
13.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block's lock status (see Section 15.2, "Read Device Identifier" on page 76). Data bits DQ[1:0] display the addressed block's lock status; DQ0 is the addressed block's lock bit, while DQ1 is the addressed block's lock-down bit.
Figure 28.
Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown 4,5 [011]
Hardware Locked 5 [011]
WP# Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control
Notes:
1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don't Care. 2. DQ1 indicates Block Lock-Down status. DQ1 = `0', Lock-Down has not been issued to this block. DQ1 = `1', Lock-Down has been issued to this block. 3. DQ0 indicates block lock status. DQ0 = `0', block is unlocked. DQ0 = `1', block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states.
13.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command.
Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error.
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If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, "Write State Machine (WSM)" on page 78, which shows valid commands during an erase suspend.
13.2
Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 29, "Protection Register Map" on page 69). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked
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.
Figure 29.
Protection Register Map
0x109 128-bit Protection Register 16 (User-Programmable) 0x102
0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-Bit Protection Register 0 64-bit Segment (Factory-Programmed)
13.2.1
Reading the Protection Registers
The Protection Registers can be read from within any partition's address space. To read the Protection Register, first issue the Read Device Identifier command at any partitions' address to place that partition in the Read Device Identifier state (see Section 9.2, "Device Commands" on page 47). Next, perform a read operation at that partition's base address plus the address offset corresponding to the register to be read. Table 17, "Device Identifier Information" on page 77 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time.
Note:
If a program or erase operation occurs within the device while it is reading a Protection Register, certain restrictions may apply. See Table 15, "Simultaneous Operation Restrictions" on page 74 for details.
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13.2.2
Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition's base address plus the offset to the desired Protection Register (see Section 9.2, "Device Commands" on page 47). Next, write the desired Protection Register data to the same Protection Register address (see Figure 29, "Protection Register Map" on page 69). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 46, "Protection Register Programming Flowchart" on page 92). Issuing the Program Protection Register command outside of the Protection Register's address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set).
Note:
If a program or erase operation occurs when programming a Protection Register, certain restrictions may apply. See Table 15, "Simultaneous Operation Restrictions" on page 74 for details.
13.2.3
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, "Device Commands" on page 47). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 17, "Device Identifier Information" on page 77). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. The other bits in Lock Register 0 are not used. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.
Caution:
After being locked, the Protection Registers cannot be unlocked.
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Intel StrataFlash(R) Wireless Memory (L18)
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition.
14.1
Memory Partitioning
The L18 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at a time can be in program or erase mode. The flash device supports read-while-write operations with bus cycle granularity and not command granularity. In other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. In practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. This is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write command's (Figure 30, and Figure 31). However, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (See Figure 32) When reading from the same partition after issuing a Setup command, Status Register data is returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 30.
Operating Mode with Correct Command Sequence Example
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
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Figure 31.
Operating Mode with Correct Command Sequence Example
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition A
Partition B
Partition A
0x20
Valid Array Data
0xD0
Figure 32.
Operating Mode with Illegal Command Sequence Example
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition A
Partition B
Partition A
Partition A
0x20
0xFF
0xD0
SR[7:0]
14.2.1
Simultaneous Operation Details
The Intel StrataFlash(R) Wireless Memory (L18) supports simultaneous read from one partition while programming or erasing in any other partition. Certain features like the Protection Registers and Query data have special requirements with respect to simultaneous operation capability. These will be detailed in the following sections.
14.2.2
Synchronous and Asynchronous RWW Characteristics and Waveforms
This section describes the transition of write operation to asynchronous read, write to synchronous read, and write operation with clock active.
14.2.2.1
Write operation to asynchronous read transition
W18 - tWHAV The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
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14.2.2.2
Write to synchronous read operation transition
W19 and W20 - tWHCV and tWHVH The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high to latch a new address must be met.
14.2.2.3
Write Operation with Clock Active
W21 - tVHWL W22 - tCHWL The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to WE# low) are required during write operations when the device is in a synchronous mode and the clock is active. A write bus cycle consists of two parts:
* the host provides an address to the flash device; and * the host then provides data to the flash device.
The flash device in turn binds the received data with the received address. When operating synchronously (RCR[15] = 0), the address of a write cycle may be provided to the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions are met between each cycle. If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (W5, tAVWH) before the rising WE# edge. Alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the current write cycle). In this case, the flash device will use the most recently provided address from the host. Refer to Figure 20, "Write to Asynchronous Read Timing" on page 39, Figure 21, "Synchronous Read to Write Timing" on page 39, and Figure 22, "Write to Synchronous Read Timing" on page 40, for representation of these timings.
14.2.3
Read Operation During Buffered Programming
The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. To perform a read while buffered programming operation, first issue a Buffered Program set up command in a partition. When a read operation occurs in the same partition after issuing a setup command, Status Register data will be returned, regardless of the read mode of the partition prior to issuing the setup command.
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To read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. However, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the Status Register. See Figure 41, "Buffer Program Flowchart" on page 87 for more details. Note: Simultaneous read-while-Buffered EFP is not supported.
14.3
Simultaneous Operation Restrictions
Since the Intel StrataFlash(R) Wireless Memory (L18) supports simultaneous read from one partition while programming or erasing in another partition, certain features like the Protection Registers and CFI Query data have special requirements with respect to simultaneous operation capability. (Table 15 provides details on restrictions during simultaneous operations.)
Table 15.
Protection Register or CFI data
Simultaneous Operation Restrictions
Parameter Partition Array Data Other Partitions Notes
Read
(See Notes)
(See Notes)
Read
Read
Read
Write
No Access Allowed
No Access Allowed
Write/Erase
While programming or erasing in a main partition, the Protection Register or CFI data may be read from any other partition. Reading the parameter partition array data is not allowed if the Protection Register or Query data is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Write/Erase Accessing the Protection Registers or CFI data from parameter partition addresses is not allowed when reading array data from the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Write/Erase Accessing the Protection Registers or CFI data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. While programming the Protection Register, reads are only allowed in the other main partitions. Read Access to array data in the parameter partition is not allowed. Programming of the Protection Register can only occur in the parameter partition, which means this partition is in Read Status. While programming or erasing the parameter partition, reads of the Protection Registers or CFI data are not allowed in any partition. Read Reads in partitions other than the parameter partition are supported. Write/Erase
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Intel StrataFlash(R) Wireless Memory (L18)
15.0
Special Read States
The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. Each partition can be in one of its read states independent of other partitions' modes. See Figure 11, "Asynchronous Single-Word Read with ADV# Low" on page 33 and Figure 14, "Synchronous Single-Word Array or Non-array Read Timing" on page 35 for details.
15.1
Read Status Register
The status of any partition is determined by reading the Status Register from the address of that particular partition. To read the Status Register, issue the Read Status Register command within the desired partition's address range. Status Register information is available at the partition address to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from a partition after any of these command sequences outputs that partition's status until another valid command is written to that partition (e.g. Read Array command). The Status Register is read using single asynchronous-mode or synchronous burst mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Status Register read operations do not affect the read state of the other partitions. The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit (SR[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-locked operations.
Table 16.
Status Register Description (Sheet 1 of 2)
Status Register (SR) Default Value = 0x80
Device Write Status DWS
7
Erase Suspend Status ESS
6
Erase Status ES
5
Program Status PS
4
VPP Status VPPS
3
Program Suspend Status PSS
2
BlockLocked Status BLS
1
Partition Status PWS
0
Bit
Name
Description
7 6
Device Write Status (DWS) Erase Suspend Status (ESS)
0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 0 = Erase suspend not in effect. 1 = Erase suspend in effect.
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Table 16.
Status Register Description (Sheet 2 of 2)
Status Register (SR) Default Value = 0x80
5 4 3 2 1
Erase Status (ES) Program Status (PS) VPP Status (VPPS) Program Suspend Status (PSS) Block-Locked Status (BLS)
0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7] 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. 0 = Program suspend not in effect. 1 = Program suspend in effect. 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. DWS PWS 0 0 = Program or erase operation in addressed partition. 0 1 = Program or erase operation in other partition. 1 0 = No active program or erase operations. 1 1 = Reserved. (Non-buffered EFP operation. For Buffered EFP operation, see Section 11.3, "Buffered Enhanced Factory Programming" on page 60).
0
Partition Write Status (PWS)
Always clear the Status Register prior to resuming erase operations. This avoids Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status.
15.1.1
Clear Status Register
The Clear Status Register command clears the status register, leaving all partition read states unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register.
15.2
Read Device Identifier
The Read Device Identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition's addresses are read (see Section 9.2, "Device Commands" on page 47 for details on issuing the Read Device Identifier command). Table 17, "Device Identifier Information" on page 77 and Table 18, "Device ID codes" on page 77 show the address offsets and data values for this device. Issuing a Read Device Identifier command to a partition that is programming or erasing places that partition in the Read Identifier state while the partition continues to program or erase in the background.
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Table 17.
Device Identifier Information
Item Address(1,2) Data
Manufacturer Code Device ID Code Block Lock Configuration: * Block Is Unlocked * Block Is Locked * Block Is not Locked-Down * Block Is Locked-Down Configuration Register Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 16x128-bit User-Programmable Protection Registers
Notes: 1. PBA = Partition Base Address. 2. BBA = Block Base Address.
PBA + 0x00 PBA + 0x01
0089h ID (see Table 18) Lock Bit: DQ0 = 0b0
BBA + 0x02
DQ0 = 0b1 DQ1 = 0b0 DQ1 = 0b1
PBA + 0x05 PBA + 0x80 PBA + 0x81-0x84 PBA + 0x85-0x88 PBA + 0x89 PBA + 0x8A-0x109
Configuration Register Data PR-LK0 Factory Protection Register Data User Protection Register Data Protection Register Data PR-LK1
Table 18.
Device ID codes
Device Identifier Codes ID Code Type Device Density -T -B (Top Parameter) (Bottom Parameter)
Device Code
64 Mbit 128 Mbit 256 Mbit
880B 880C 880D
880E 880F 8810
15.3
CFI Query
The CFI Query command instructs the device to output Common Flash Interface (CFI) data when partition addresses are read. See Section 9.2, "Device Commands" on page 47 for details on issuing the CFI Query command. Appendix C, "Common Flash Interface" on page 93 shows CFI information and address offsets within the CFI database. Issuing the CFI Query command to a partition that is programming or erasing places that partition's outputs in the CFI Query state, while the partition continues to program or erase in the background. The CFI Query command is subject to read restrictions dependent on parameter partition availability, as described in Table 15.
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Appendix A Write State Machine (WSM)
Figure 33 through Figure 38 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition's output state.
Figure 33.
Write State Machine--Next State Table (Sheet 1 of 6)
Command Input to Chip and resulting Chip Next State
Read Array (2) Word Program (3,4) Buffered Program (BP) Erase Setup (3,4) Buffered Enhanced Factory Pgm Setup (3, 4) (20H) Erase Setup (80H) BEFP Setup Ready (Unlock Block) OTP Busy Word Program Busy Program Busy Word Program Busy BP Load 1 BP Load 2 Word Program Suspend Word Program Busy BE Confirm, P/E Resume, ULB, Confirm (8) (D0H) BP / Prg / Erase Suspend Read Status Clear Status Register
(5)
Current Chip State (7)
Read ID/Query
Lock, Unlock, Lock-down, CR setup (4)
(FFH) Ready Ready
(10H/40H) Program Setup
(E8H) BP Setup
(B0H)
(70H) Ready
(50H)
(90H, 98H)
(60H) Lock/CR Setup
Lock/CR Setup Setup Busy Setup Word Program Busy
Ready (Lock Error)
Ready (Lock Error)
OTP
Suspend Setup BP Load 1
Word Program Suspend
Word Program Suspend
BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend Erase Suspend Word Program Setup in Erase Suspend Ready (Error)
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP Busy
Ready (Error)
BP Busy BP Suspend Ready (Error) Erase Busy BP Busy Erase Busy
BP Suspend
BP Busy BP Suspend Ready (Error)
Erase Suspend
Erase Busy Lock/CR Setup in Erase Suspend
BP Setup in Erase Suspend
Erase Suspend
Erase Busy
Erase Suspend
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Figure 34.
Write State Machine--Next State Table (Sheet 2 of 6)
Command Input to Chip and resulting Chip Next State
Read (2) Array Word (3,4) Program Buffered Program (BP) Buffered Enhanced Erase (3,4) Factory Pgm Setup (3, 4) Setup (20H) (80H) BE Confirm, P/E Resume, ULB, Confirm (D0H)
(8)
Current Chip State (7)
BP / Prg / Erase Suspend
Read Status
Clear Status (5) Register
Read ID/Query
Lock, Unlock, Lock-down, (4) CR setup
(FFH)
Setup
(10H/40H)
(E8H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
Word Program Busy in Erase Suspend Word Program Suspend in Erase Suspend Word Program Busy in Erase Suspend BP Load 1 BP Load 2
Word Program in Erase Suspend
Busy
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Suspend
Word Program Suspend in Erase Suspend
Word Program Suspend in Erase Suspend
Setup BP Load 1
BP Load 2
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP in Erase Suspend
BP Confirm
Erase Suspend (Error)
BP Busy in Erase Suspend BP Suspend in Erase Suspend BP Busy in Erase Suspend Erase Suspend (Unlock Block) BEFP Loading Data (X=32)
Ready (Error in Erase Suspend)
BP Busy
BP Busy in Erase Suspend
BP Busy in Erase Suspend
BP Suspend
BP Suspend in Erase Suspend
BP Suspend in Erase Suspend
Lock/CR Setup in Erase Suspend
Erase Suspend (Lock Error)
Erase Suspend (Lock Error [Botch])
Buffered Enhanced Factory Program Mode
Setup
Ready (Error)
Ready (Error)
BEFP Busy
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
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Figure 35.
Write State Machine--Next State Table (Sheet 3 of 6)
Command Input to Chip and resulting Chip Next State
OTP Setup (4) Lock Block Confirm
(8)
Current Chip State (7)
Lock-Down Block Confirm
(8)
Write RCR Confirm (8)
Block Address (?WA0) 9
Illegal Cmds or BEFP Data (1)
WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H) Ready
(XXXXH)
(all other codes)
Ready
OTP Setup Ready (Lock Error) Ready (Lock Block) Ready (Lock Down Blk)
Lock/CR Setup Setup Busy Setup Word Program Busy
Ready (Set CR) OTP Busy
Ready (Lock Error)
N/A
OTP
Ready N/A Ready
Word Program Busy Word Program Busy
Suspend Setup BP Load 1
BP Load 2
Word Program Suspend BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; ELSE BP Load 2 N/A
BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend
BP Confirm if Data load into Program Buffer is complete; ELSE BP load 2
Ready
Ready (Error)
Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Suspend
Ready (Error)
Ready
N/A Ready (Error) Erase Busy Ready
Erase Suspend
N/A
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Figure 36.
Write State Machine--Next State Table (Sheet 4 of 6)
Command Input to Chip and resulting Chip Next State
OTP Setup (4) Lock Block Confirm (8) Lock-Down Block Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1)
Current Chip State (7)
WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H)
(XXXXH)
(all other codes)
Setup
Word Program Busy in Erase Suspend
NA
Word Program in Erase Suspend
Busy
Word Program Busy in Erase Suspend Busy
Erase Suspend
Suspend
Word Program Suspend in Erase Suspend
N/A
Setup BP Load 1
BP Load 2
BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP Load 2
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
Ready
N/A
BP in Erase Suspend
BP Confirm
Ready (Error in Erase Suspend)
Ready (Error) (Proceed if unlocked or lock error)
Ready (Error)
BP Busy
BP Busy in Erase Suspend
Erase Suspend
BP Suspend
Erase Suspend (Lock Error) Erase Suspend (Lock Block)
BP Suspend in Erase Suspend
Lock/CR Setup in Erase Suspend
Erase Suspend (Lock Down Block)
Erase Suspend (Set CR)
Erase Suspend (Lock Error)
N/A
Buffered Enhanced Factory Program Mode
Setup
Ready (Error)
Ready (BEFP Loading Data)
Ready (Error)
BEFP Busy
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
Ready
BEFP Busy
Ready
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Figure 37.
Write State Machine--Next State Table (Sheet 5 of 6)
Output Next State Table
Command Input to Chip and resulting Output Mux Next State
Word Program Setup (3,4) BE Confirm, Buffered P/E Enhanced Resume, Factory Pgm ULB Confirm (3, 4) Setup (8) (30H) (D0H) Program/ Erase Suspend Clear Status Register
(5)
Read
Current chip state
Array
(2)
BP Setup
Erase Setup
(3,4)
Read Status
Read ID/Query
Lock, Unlock, Lock-down, CR setup
(4)
(FFH)
(10H/40H)
(E8H)
(20H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend
Status Read
Status Read
Status Read
Read Array
Status Read
Output does not change.
Status Read
Output mux does not change.
Status Read ID Read
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Figure 38.
Write State Machine--Next State Table (Sheet 6 of 6)
Output Next State Table
Command Input to Chip and resulting Output Mux Next State
Lock Block Confirm (8) Lock-Down Block Confirm (8)
OTP
Write CR Confirm
(8)
Current chip state
Setup
(4)
Block Address (?WA0)
Illegal Cmds or BEFP Data
(1)
WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H)
(FFFFH)
(all other codes)
BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend
Status Read
Status Read
Array Read
Status Read Output does not change.
Status Read
Output does not change.
Array Read
Output does not change.
Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/
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5. 6. 7. 8. 9.
resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. WA0 refers to the block address latched during the first write cycle of the current operation.
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Appendix B Flowcharts
Figure 39. Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Bus Operation Command Write
(Setup)
Comments
Write 0x40, Word Address Write Data, Word Address Read Status Register
Program Data = 0x40 Setup Addr = Location to program Data Data = Data to program Addr = Location to program Status register data Check SR[7] 1 = WSM Ready 0 = WSM Busy
Write
(Confirm)
Read Program Suspend Loop
No Yes
None
Idle
None
SR[7] =
1
0
Suspend?
Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set to the Read Array state.
Full Status Check (if desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Idle SR[3] =
0 1 1
Comments Check SR[3]: 1 = VPP Error Check SR[4]: 1 = Data Program Error Check SR[1]: 1 = Block locked; operation aborted
None
VPP Range Error Idle Program Error None
SR[4] =
0
Idle
None
SR[1] =
0
1
Device Protect Error
If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register command clears the Status Register error bits.
Program Successful
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Figure 40.
Program Suspend/Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Start
Program Suspend
Write B0h Any Address
Read Status
Bus Operation Command Write
Comments
Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status Data = 70h Addr = Same partition Status register data Addr = Suspended block (BA) Check SR.7 1 = WSM ready 0 = WSM busy Check SR.2 1 = Program suspended 0 = Program completed Read Array Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Program Data = D0h Resume Addr = Suspended block (BA)
Write 70h Same Partition Read Status Register
Write
Read
SR.7 =
1
0
Standby
SR.2 =
1 Read Array
0
Program Completed
Standby
Write
Write FFh Susp Partition Read Read Array Data
Write
No
Done Reading
Yes Program Resume
If the suspended partition was placed in Read Array mode: Write
Read Array
Read Status
Return partition to Status mode: Data = 70h Addr = Same partition
Write D0h Any Address Program Resumed
Read Status
Write FFh Pgm'd Partition Read Array Data
Write 70h Same Partition
PGM_SUS.WMF
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Figure 41.
Buffer Program Flowchart
Buffer Programming Procedure
Start Bus Operation Device Supports Buffer Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Buffer Prog. Cmd. 0xE8, Word Address No Use Single Word Programming Write Read Command Buffer Prog. Setup None Comments Data = 0xE8 Addr = Word Address SR[7] = Valid Addr = Word Address Check SR[7]: 1 = Write Buffer available 0 = No Write Buffer available Data = N-1 = Word Count N = 0 corresponds to count = 1 Addr = Word Address Data = Write Buffer Data Addr = Start Word Address Data = Write Buffer Data Addr = Word Address Data = 0xD0 Addr = Original Word Address Status register Data Addr = Note 7 Check SR[7]: 1 = WSM Ready 0 = WSM Busy
Idle
None
Write (Notes 1, 2) Write (Notes 3, 4) Write (Note 3) Write (Notes 5, 6) Read Yes Idle
None
None None Buffer Prog. Conf. None
Other partitions of the device can be read by addressing those partitions and driving OE# low. (Any write commands are not allowed during this period.)
Read Status Register at Word Address No Write Buffer Available? SR[7] = 1 = Yes Write Word Count, Word Address Buffer Program Data, Start Word Address 0 = No Timeout or Count Expired?
None
X=X+1
X=0
Write Buffer Data, Word Address No No Abort Buffer Program? Yes
X = N?
Yes Write Confirm 0xD0 and Word Address (Note 5)
Write to another Block Address
1. Word count value on D[7:0] is loaded into the word count register. Count ranges for this device are N = 0x00 to 0x1F. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the issued word address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A[4:0] of the Start Word Address = 0x00). 5. The Buffered Programming Confirm command must be issued to an address in the same block, for example, the original Start Word Address, or the last address used during the loop that loaded the buffer data. 6. The Status Register indicates an improper command sequence if the Buffer Program command is aborted; use the Clear Status Register command to clear error bits. 7. The Status Register can be read from any addresses within the programming partition. Full status check can be done after all erase and write sequences complete. Write 0xFF after the last operation to place the partition in the Read Array state.
0xFF commands can be issued to read from any blocks in other partitions
Buffer Program Aborted
Issue Read Status Register Command
Read Status Register (Note 7) No 0=No Suspend Program? Yes
Suspend Program Loop
Is BP finished? SR[7] =
1=Yes Full Status Check if Desired
Program Complete
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 42.
Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Start
Program & Verify Phase
Read Status Reg.
Exit Phase
Read Status Reg.
VPP applied, Block unlocked
No (SR[0]=1)
Data Stream Ready? Yes (SR[0]=0) Initialize Count: X=0
No (SR[7]=0)
BEFP Exited? Yes (SR[7]=1) Full Status Check Procedure
Write 0x80 @ 1ST Word Address
Write 0xD0 @ 1ST Word Address
Write Data @ 1ST Word Address
Program Complete
BEFP setup delay
Increment Count: X = X+1
Read Status Reg. N X = 32? Y Read Status Reg. No (SR[0]=1) Program Done? Yes (SR[0]=0) N Last Data? Y Write 0xFFFF, Address Not within Current Block BEFP Setup Bus State Write Write (Note 1) Write Read Operation Unlock Block BEFP Setup BEFP Confirm Status Register BEFP Setup Done? Comments V PPH applied to VPP
ST Data = 0x80 @ 1 Word Address
BEFP Setup Done?
Yes (SR[7]=0)
No (SR[7]=1) Check VPP, Lock Errors (SR[3,1])
Exit
BEFP Program & Verify Bus State Operation Read Status Register Comments Data = Status Register Data Address = 1ST Word Addr. Bus State Read
BEFP Exit Operation Status Register Comments Data = Status Reg. Data Address = 1ST Word Addr
Data = 0xD0 @ ST Word Address1 Data = Status Reg. Data Address = 1ST Word Addr Check SR[7]: 0 = BEFP Ready 1 = BEFP Not Ready
Check SR[0]: Data Stream Standby 0 = Ready for Data Ready? 1 = Not Ready for Data Standby Write (Note 2) Standby Initialize Count Load Buffer Increment Count Buffer Full? Status Register Program Done? Last Data? X=0 Data = Data to Program Address = 1ST Word Addr. X = X+1 X = 32? Yes = Read SR[0] No = Load Next Data Word Data = Status Reg. data Address = 1ST Word Addr. Check SR[0]: 0 = Program Done 1 = Program in Progress No = Fill buffer again Yes = Exit
Standby
Check SR[7]: Check Exit 0 = Exit Not Completed Status 1 = Exit Completed
Repeat for subsequent blocks; After BEFP exit, a full Status Register check can determine if any program error occurred; See full Status Register check procedure in the Word Program flowchart. Write 0xFF to enter Read Array state.
Standby
Error If SR[7] is set, check: Standby Condition SR[3] set = VPP Error SR[1] set = Locked Block Check
Standby
Read
Standby
Standby
Write
Exit Prog & Data = 0xFFFF @ address not in Verify Phase current block
NOTES: 1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary. 2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address; WSM internally increments addressing.
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 43.
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Bus Command Comments Operation Block Data = 0x20 Erase Write Addr = Block to be erased (BA) Setup Write Write 0xD0, (Erase Confirm) Block Address Read Read Status Register
No
Write 0x20, (Block Erase) Block Address
Erase Data = 0xD0 Confirm Addr = Block to be erased (BA) None Status Register data. Check SR[7]: 1 = WSM ready 0 = WSM busy
Suspend Erase Loop Suspend Erase
Idle
None
SR[7] =
1
0
Yes
Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode.
Full Erase Status Check (if desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register
1
Bus Command Operation Idle None None None VPP Range Error Command Sequence Error Block Erase Error Block Locked Error
Comments Check SR[3]: 1 = VPP Range Error Check SR[4,5]: Both 1 = Command Sequence Error Check SR[5]: 1 = Block Erase Error Check SR[1]: 1 = Attempted erase of locked block; erase aborted.
SR[3] =
0
Idle Idle
SR[4,5] =
0
1,1
SR[5] =
0
1
Idle
None
Only the Clear Status Register command clears SR[1, 3, 4, 5].
1
SR[1] =
0
If an error is detected, clear the Status register before attempting an erase retry or other error recovery.
Block Erase Successful
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Figure 44.
Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus Command Operation
(Read Status)
Comments Data = 0x70 Addr = Any partition address Data = 0xB0 Addr = Same partition address as above Status Register data. Addr = Same partition Check SR[7]: 1 = WSM ready 0 = WSM busy Check SR[6]: 1 = Erase suspended 0 = Erase completed
Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register
Write
Read Status Erase Suspend None
(Erase Suspend)
Write
Read
Idle SR[7] =
1 0 0
None
Idle Erase Completed Write Read or Write Write
None
SR[6] =
1
Read Array Data = 0xFF or 0x40 Addr = Any address within the or Program suspended partition None Read array or program data from/to block other than the one being erased
Read
Read or Program?
No
Program
Read Array Data
Program Loop
Program Data = 0xD0 Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Read Status Register Return partition to Status mode: Data = 0x70 Addr = Same partition
Done
(Erase Resume)
Write 0xD0, Any Address Erase Resumed Write 0x70, Same Partition
Write
Write 0xFF, (Read Array) Erased Partition Read Array Data
(Read Status)
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Intel StrataFlash(R) Wireless Memory (L18)
Figure 45.
Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Bus Command Operation
(Lock Setup)
Comments Data = 0x60 Addr = Block to lock/unlock/lock-down
Write 0x60, Block Address
Write
Lock Setup
Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address
Write
Lock, Data = 0x01 (Block Lock) Unlock, or 0xD0 (Block Unlock) Lock-Down 0x2F (Lock-Down Block) Confirm Addr = Block to lock/unlock/lock-down
Write 0x90
(Read Device ID)
Write Read Data = 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data (Optional) Status Addr = Block address + offset 2
Optional
Read Block Lock Status
Locking Change?
Yes
No
Idle
None
Confirm locking change on D[1,0].
Write
Read Array
Data = 0xFF Addr = Block address
Write 0xFF (Read Array) Partition Address Lock Change Complete
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Figure 46.
Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start Bus Command Operation Write
(Program Setup)
Comments
Write 0xC0, PR Address
Program Data = 0xC0 PR Setup Addr = First Location to Program Protection Data = Data to Program Program Addr = Location to Program None Status Register Data. Check SR[7]: 1 = WSM Ready 0 = WSM Busy
Write Write PR Address & Data
(Confirm Data)
Read
Read Status Register
Idle
None
SR[7] =
1
0
Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations.
Full Status Check (if desired) Program Complete
Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set Read Array state.
FULL STATUS CHECK PROCEDURE
Read Status Register Data Bus Command Operation Idle SR[3] =
0 1 1
Comments Check SR[3]: 1 =VPP Range Error Check SR[4]: 1 =Programming Error Check SR[1]: 1 =Block locked; operation aborted
None
VPP Range Error Idle None
SR[4] =
0
Program Error
Idle
None
Only the Clear Staus Register command clears SR[1, 3, 4].
1
SR[1] =
0
Register Locked; Program Aborted
If an error is detected, clear the Status register before attempting a program retry or other error recovery.
Program Successful
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Appendix C Common Flash Interface
The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, "Device Commands" on page 47). System software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device.
C.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ7-0) and 00h in the high byte (DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 19.
Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset Hex Code ASCII Value
00010: Device Addresses 00011: 00012:
51 52 59
"Q" "R" "Y"
Table 20.
Example of Query Structure Output of x16- Devices
Datasheet
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Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ...
Word Addressing: Hex Code D15-D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ...
Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ...
Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ...
Byte Addressing: Hex Code D7-D0 51 52 59 P_IDLO P_IDLO P_IDHI ...
Value "Q" "R" "Y" PrVendor ID # ID # ...
C.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized in Table 21.
Table 21.
Query Structure
Offset 00001-Fh 00010h 0001Bh 00027h P(3) Description(1) Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Primary Intel-specific Extended Query Table Vendor-defined additional information specific Sub-Section Name
Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 16-Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
C.3
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 22.
CFI Identification
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Intel StrataFlash(R) Wireless Memory (L18)
Offset 10h
Length 3
Description Query-unique ASCII string "QRY"
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --01 14: --00 15: --0A 16: --01 17: --00 18: --00 19: --00 1A: --00
Table 23.
System Interface Information
Offset 1Bh Length 1 Description Hex Add. Code 1B: --17
1Ch
1
1Dh
1
1Eh
1
1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage 1D: bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage 1E: bits 0-3 BCD 100 mV bits 4-7 HEX volts 1F: "n" such that typical single word program time-out = 2n -sec 20: "n" such that typical max. buffer write time-out = 2n -sec 21: "n" such that typical block erase time-out = 2n m-sec 22: "n" such that typical full chip erase time-out = 2n m-sec "n" such that maximum word program time-out = 2n times typical 23: 24: "n" such that maximum buffer write time-out = 2n times typical 25: "n" such that maximum block erase time-out = 2n times typical 26: "n" such that maximum chip erase time-out = 2n times typical
Value 1.7V
--20
2.0V
--85
8.5V
--95
9.5V
--08 --09 --0A --00 --01 --01 --02 --00
256s 512s 1s NA 512s 1024s 4s NA
C.4
Table 24.
Device Geometry Definition
Device Geometry Definition
Datasheet
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Offset 27h
Length Description "n" such that device size = 2n in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table:
7 6 5 4 3 2 1 0
Code 27:
See table below
28h
2
--
15
--
14
--
13
--
12
x64
11
x32
10
x16
9
x8
8
28: 29: 2A: 2B: 2C:
--01 --00 --06 --00
x16
2Ah 2Ch
2 1
-- -- -- -- -- -- -- -- "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information
64
See table below
2Dh
4
31h
4
35h
4
2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
See table below
See table below
See table below
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38: -B --17 --01 --00 --06 --00 --02 --03 --00 --80 --00 --3E --00 --00 --02 --00 --00 --00 --00
64 Mbit -T --17 --01 --00 --06 --00 --02 --3E --00 --00 --02 --03 --00 --80 --00 --00 --00 --00 --00
128 Mbit -B -T --18 --18 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --7E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00
256 Mbit -B -T --19 --19 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --FE --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
C.5
Table 25.
Intel-Specific Extended Query Table
Primary Vendor-Specific Extended Query
Description Offset(1) Length P = 10Ah (Optional flash features and commands) (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string "PRI" (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional feature and command support (1=yes, 0=no) (P+6)h bits 10-31 are reserved; undefined bits are "0." If bit 31 is (P+7)h "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. (P+8)h bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported Supported functions after suspend: read Array, Status, Query (P+9)h 1 Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend 2 Block status register mask (P+A)h bits 2-15 are Reserved; undefined bits are "0" (P+B)h bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active (P+C)h 1 VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage (P+D)h 1 bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Add. 10A 10B: 10C: 10D: 10E: 10F: 110: 111: 112: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 113: Hex Code --50 --52 --49 --31 --33 --E6 --03 --00 --00 =0 =1 =1 =0 =0 =1 =1 =1 =1 =1 --01 Value "P" "R" "I" "1" "3"
No Yes Yes No No Yes Yes Yes Yes Yes
bit 0 114: 115: bit 0 bit 1 116:
=1 --03 --00 =1 =1 --18
Yes
Yes Yes 1.8V
117:
--90
9.0V
Datasheet
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Table 26.
Protection Register Information
Description Offset(1) Length P = 10Ah (Optional flash features and commands) (P+E)h 1 Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection fields are available (P+F)h 4 Protection Field 1: Protection Description (P+10)h This field describes user-available One Time Programmable (P+11)h (OTP) Protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user (P+12)h programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes Jedec-plane physical low address bits 8-15 = Lock/bytes Jedec-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h 10 Protection Field 2: Protection Description Bits 0-31 point to the Protection register physical Lock-word address in the Jedec-plane. Following bytes are factory or user-programmable. bits 32-39 = "n" n = factory pgm'd groups (low byte) bits 40-47 = "n" n = factory pgm'd groups (high byte) bits 48-55 = "n" \ 2n = factory programmable bytes/group bits 56-63 = "n" n = user pgm'd groups (low byte) bits 64-71 = "n" n = user pgm'd groups (high byte) bits 72-79 = "n" 2n = user programmable bytes/group 11D: 11E: 11F: 120: 121: 122: 123: 124: 125: 126: --89 --00 --00 --00 --00 --00 --00 --10 --00 --04 89h 00h 00h 00h 0 0 0 16 0 16 Hex Add. Code 118: --02 119: 11A: 11B: 11C: --80 --00 --03 --03 Value 2 80h 00h 8 byte 8 byte
Table 27.
Burst Read Information
Description Offset(1) Length P = 10Ah (Optional flash features and commands) (P+1D)h 1 Page Mode Read capability bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that (P+1E)h 1 follow. 00h indicates no burst capability. (P+1F)h 1 Synchronous mode read capability configuration 1 Bits 3-7 = Reserved bits 0-2 "n" such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. (P+20)h 1 Synchronous mode read capability configuration 2 (P+21)h 1 Synchronous mode read capability configuration 3 (P+22)h 1 Synchronous mode read capability configuration 4 Hex Add. Code Value 127: --03 8 byte
128: 129:
--04 --01
4 4
12A: 12B: 12C:
--02 --03 --07
8 16 Cont
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Table 28.
(1)
Partition and Erase-block Region Information
See table below Address Bot Top Len 1 12D: 12D:
Offset P= 10Ah Description Bottom Top (Optional flash features and commands) (P+23)h (P+23)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
Datasheet
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Table 29.
Partition Region 1 Information
Offset P = 10Ah Description Bottom Top (Optional flash features and commands) (P+24)h (P+24)h Number of identical partitions within the partition region (P+25)h (P+25)h (P+26)h (P+26)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+27)h (P+27)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+28)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+29)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+2A)h Partition Region 1 Erase Block Type 1 Information (P+2B)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+2C)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+2D)h (P+2E)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+2F)h (P+30)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+31)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use Partition Region 1 Erase Block Type 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes (bottom parameter device only) Partition 1 (Erase block Type 2) Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use Partition 1 (Erase block Type 2) pagemode and synchronous mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use
(1)
See table below Address Bot Top Len 2 12E: 12E: 12F: 12F: 1 130: 130:
1
131:
131:
(P+28)h
1
132:
132:
(P+29)h
1
133:
133:
(P+2A)h (P+2B)h (P+2C)h (P+2D)h (P+2E)h (P+2F)h (P+30)h
4
2 1
134: 135: 136: 137: 138: 139: 13A:
134: 135: 136: 137: 138: 139: 13A:
(P+31)h
1
13B:
13B:
(P+32)h (P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h
4
2 1
13C: 13D: 13E: 13F: 140: 141: 142:
(P+39)h
1
143:
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
Table 30.
Partition Region 2 Information
Offset(1) P = 10Ah Description Bottom Top (Optional flash features and commands) (P+3A)h (P+32)h Number of identical partitions within the partition region (P+3B)h (P+33)h (P+3C)h (P+34)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3D)h (P+35)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3E)h (P+36)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3F)h (P+37)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information (P+41)h (P+39)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+42)h (P+3A)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+3B)h (P+44)h (P+3C)h Partition 2 (Erase block Type 1) (P+45)h (P+3D)h Minimum block erase cycles x 1000 (P+46)h (P+3E)h Partition 2 (Erase block Type 1) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+47)h (P+3F)h Partition 2 (erase block Type 1) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+40)h Partition Region 2 Erase Block Type 2 Information (P+41)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+42)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+44)h Partition 2 (Erase block Type 2) (P+45)h Minimum block erase cycles x 1000 (P+46)h Partition 2 (Erase block Type 2) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+47)h Partition 2 (erase block Type 2) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use See table below Address Bot Top Len 2 144: 13C: 145: 13D: 1 146: 13E:
1
147:
13F:
1
148:
140:
1
149:
141:
4
2 1
14A: 14B: 14C: 14D: 14E: 14F: 150:
142: 143: 144: 145: 146: 147: 148:
1
151:
149:
4
2 1
14A: 14B: 14C: 14D: 14E: 14F: 150:
1
151:
Datasheet
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Intel StrataFlash(R) Wireless Memory (L18)
Table 31.
Partition and Erase Block Region Information
Address 12D: 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A: 13B: 13C: 13D: 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 14B: 14C: 14D: 14E: 14F: 150: 151: -B --02 --01 --00 --11 --00 --00 --02 --03 --00 --80 --00 --64 --00 --02 --03 --06 --00 --00 --02 --64 --00 --02 --03 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --03 64 Mbit -T --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --03 --01 --00 --11 --00 --00 --02 --06 --00 --00 --02 --64 --00 --02 --03 --03 --00 --80 --00 --64 --00 --02 --03 128 Mbit -B -T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --07 --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --03 --03 --06 --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --06 --03 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --03 --07 --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --03 --03 256 Mbit -B -T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --0F --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --03 --03 --0E --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --0E --03 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --03 --0F --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --03 --03
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Intel StrataFlash(R) Wireless Memory (L18)
Appendix D Additional Information
Order/Document Number
Document/Tool
251903 290701 290702 290737 251908 251909 298161 297833 298136
Intel StrataFlash(R) Wireless Memory (L30) Datasheet Intel(R) Wireless Flash Memory (W18) Datasheet Intel(R) Wireless Flash Memory (W30) Datasheet Intel StrataFlash(R) Synchronous Memory (K3/K18) Datasheet Migration Guide for 1.8 Volt Intel(R) Wireless Flash Memory (W18/W30) to 1.8 Volt Intel StrataFlash(R) Wireless Memory (L18/L30), Application Note 753 Migration Guide for 3 Volt Synchronous Intel StrataFlash(R) Memory (K3/K18) to 1.8 Volt Intel StrataFlash(R) Wireless Memory (L18/L30), Application Note 754 Intel(R) Flash Memory Chip Scale Package User's Guide Intel(R) Flash Data Integrator (FDI) User's Guide Intel(R) Persistent Storage Manager User Guide
Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash(R) memory, visit our website at http:// developer.intel.com/design/flash/isf.
Datasheet
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Appendix E Ordering Information
E.1
Figure 47.
Ordering Information for VF BGA Package
Ordering Information for L18 in VF BGA
GE28F640L18T85
Package Designator Expanded Temperature (-25 C to +85 C)
GE = leaded, 0.75mm VF BGA PH = lead-free, 0.75mm VF BGA
Access Speed (ns)
85
Parameter Location Product Line Designator
for all Intel Flash products
(R)
T = Top Parameter Blocking B = Bottom Parameter Blocking
Device Density
640 =x16 (64-Mbit) 128 =x16 (128-Mbit) 256 =x16 (256-Mbit)
Product Family
L18 = Intel Strataflash(R) Wireless Memory V CC = 1.7 V - 2.0 V V CCQ = 1.35 V - 2.0 V or 1.7 V -2.0 V
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Datasheet
Intel StrataFlash(R) Wireless Memory (L18)
E.2
Ordering Information for SCSP
Figure 48 and Table 32 show the ordering information for the Intel StrataFlash(R) wireless memory in QUAD+ ballout products.
Figure 48.
Ordering Information for L18 in QUAD+
Flash Family 1/2 Flash Family 3/4
Flash #1
Flash #2
Flash #3
NZ 4 8 F 4 0 0 0 L 0YBQ0
Package Designator
NZ = Intel(R) SCSP, leaded JZ = Intel(R) SCSP, lead-free
Flash #4
Device Details
0 = Original version of the products (refer to the latest version of the datasheet for details).
Product Line Designator
48F = Flash Memory only
Flash Density
0 = No die 3 = 128-Mbit 4 = 256-Mbit
Pinout Indicator
Q = QUAD+ ballout B = x16D Performance
Parameter Location
B = Bottom Parameter T = Top Parameter
Product Family
L = Intel StrataFlash(R) Wireless Family Memory 0 = No die
Voltage
Z = 3.0 V I/O Y = 1.8 V I/O
Table 32.
I/O Voltage (V)
L18 SCSP Package Ordering Information
Flash Component RAM Component Density in Mbit and Type Size (mm) Package Part Order Number
Density in Mbit and Family
Ball Type
Type
128 L18 128 L18 1.8 256 L18 256 L18
0 0 0 0
8x10x1.2 8x10x1.2 8x11x1.0 8x11x1.0
Leaded Lead-Free Leaded Lead-Free
QUAD+ SCSP QUAD+ SCSP QUAD+ SCSP QUAD+ SCSP
NZ48F3000L0YTQ0 NZ48F3000L0YBQ0 JZ48F3000L0YTQ0 JZ48F3000L0YBQ0 NZ48F4000L0YTQ0 NZ48F4000L0YBQ0 JZ48F4000L0YTQ0 JZ48F4000L0YBQ0
Datasheet
Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
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Intel StrataFlash(R) Wireless Memory (L18) Order Number: 251902, Revision: 009
Datasheet

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